Boots – shoes – and leggings
Patent
1982-09-30
1985-06-11
Malzahn, David H.
Boots, shoes, and leggings
G06F 750
Patent
active
045232920
ABSTRACT:
A binary ADDER stage for producing SUM and Carry signals is constructed with five transistors, an exclusive OR gate and an exclusive NOR gate. The two digits to be added are applied to the exclusive OR gate, the output of which is connected to one input of the exclusive NOR gate and to the gate electrode of a first N-type transistor. The second input of the exclusive NOR gate is connected to a carry input terminal, and the output of the exclusive NOR provides the sum of the two digits plus the carry. The conduction path of the first N-type transistor is connected between the carry input and carry output terminals and is conditioned to conduct when the input digits differ. Second and third N-type transistors are serially connected between the carry out terminal and ground reference and have respective gate electrodes connected to the two digit input terminals respectively, for clamping the carry out terminal to a logic 0 whenever both input digits are logical 1's. Fourth and fifth P-type transistors are serially connected between the carryout terminal and positive supply potential and have respective gate electrodes connected to the two digit input terminals, respectively, for clamping the carry output terminal to a logic 1 whenever both input digits are logical 0's.
REFERENCES:
patent: 3900742 (1975-08-01), Hampel et al.
patent: 3949242 (1976-04-01), Hirasawa et al.
patent: 4152775 (1979-05-01), Schwartz
patent: 4217502 (1980-08-01), Suzuki et al.
patent: 4255723 (1981-03-01), Ebihara
patent: 4323982 (1982-04-01), Eichrodt et al.
patent: 4357675 (1980-08-01), Freyman
patent: 4417316 (1983-11-01), Best
patent: 4425623 (1984-01-01), Russell
patent: 4439835 (1984-03-01), Best et al.
patent: 4471454 (1984-09-01), Dearden et al.
T. Kilburn et al., "Parallel Addition in Digital Computers: A New Fast Carry Circuit," IEE Proc., vol. 106, Pt. B, pp. 464-466, 1959.
T. Kilburn et al., "Parallel Arithmetic Unit Using Saturated-Transistor Fast-Carry Circuit," IEE Proc., Pt. B, vol. 107, Nov. 1960, pp. 573-584.
Herrmann E. P.
Malzahn David H.
Rasmussen P. J.
RCA Corporation
Whitacre E. M.
LandOfFree
Complementary FET ripple carry binary adder circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Complementary FET ripple carry binary adder circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Complementary FET ripple carry binary adder circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1187076