Complementary FET circuit having merged enhancement/depletion FE

Details Complementary FET circuit having merged enhancement/depletion FE Complementary FET circuit having merged enhancement/depletion FE

1989-04-21

1990-09-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307450, 307542, 307544, 307581, 307585, 3072965, H03K 19094, H03K 1712, H03K 19092, H03K 17687

Patent

active

049547305

ABSTRACT:
A merged enhancement/depletion-mode FET circuit and a complementary FET logic circuit have enhanced operation speed and reduced power dissipation. Serially connected depletion mode and enhancement mode transistors function as an output stage for the complementary FET logic stage, with the gate of an n-channel enhancement-mode transistor being connected to the output of the complementary FET logic stage and the output of an n-channel depletion-mode transistor being connected to the common terminal or output terminal of the output stage. In an alternative embodiment, a p-channel enhancement-mode transistor is connected in parallel with the n-channel depletion-mode transistor with the gate of the p-channel enhancement-mode transistor being connected to the output of the complementary FET logic stage. The circuitry is particularly useful in compound semiconductor circuits using MESFETS and heterojunction-FETs.

REFERENCES:
patent: 4463270 (1984-07-01), Gordon
patent: 4479067 (1984-10-01), Fujita
patent: 4553043 (1985-11-01), Parker
patent: 4724342 (1988-02-01), Sato et al.
patent: 4725743 (1988-02-01), Anderson et al.
patent: 4725746 (1988-02-01), Segawa et al.
patent: 4767950 (1988-08-01), Schrenk
patent: 4798978 (1989-01-01), Lee et al.
patent: 4877976 (1989-10-01), Lach et al.
patent: 4885479 (1989-12-01), Oritani

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