Complementary decode circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307455, 307456, H03K 19086, H03K 1920, H03K 19013

Patent

active

044940173

ABSTRACT:
The decode circuit utilizes NPN and PNP transistors and performs a complete decode function in only one logic level with the no need for a true/complement input of each binary input. A first embodiment of the decoder provides an UP level output when selected. A second embodiment of the decoder provides a DOWN level output when selected. The decode circuit may be used as an address decode circuit in a memory and also portion(s) of the decode circuit may be used independently as a binary logic circuit. Also disclosed is a complementary current switch logic circuit with dual phase outputs.

REFERENCES:
patent: 2964652 (1960-12-01), Yourke
patent: 2994852 (1961-08-01), Schmookler
patent: 3040192 (1962-06-01), Slobodzinski
patent: 3259761 (1966-07-01), Narud et al.
patent: 3914620 (1975-10-01), Millhollan et al.
patent: 3916215 (1975-10-01), Gaskill, Jr. et al.
patent: 4039867 (1977-08-01), Blumberg et al.
patent: 4195358 (1980-03-01), Yuen
patent: 4207556 (1980-06-01), Sugiyama et al.
patent: 4287435 (1981-09-01), Cavaliere et al.
patent: 4355245 (1982-10-01), Isogai
IBM TDB "Circuit for Generating Complementary Control Signals" by A. Brunin, vol. 21, No. 1, Jun. 1978, pp. 211-212.
IBM TDB "Self-Biased, Low Voltage, Emitter-Followerless Current Switch" by R. J. Blumberg et al., vol. 16, No. 3, Aug. 1973, p. 1017.
IBM TDB "Control Signal Generator" by A. Brunin, vol. 21, No. 1, Jun. 1978, pp. 209-210.

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