Complementary data line driver circuits with conditional...

Details Complementary data line driver circuits with conditional... Complementary data line driver circuits with conditional...

2001-10-19

2003-04-15

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S057000, C365S205000

Reexamination Certificate

active

06549042

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and, more particularly, to methods and apparatus for saving power in digital integrated circuits when driving complementary data lines.
BACKGROUND OF THE INVENTION
Many digital integrated circuit devices include pairs of complementary data lines that provide differential digital data signals to and from circuits and devices therein. In integrated circuit memory devices, these complementary data lines may take the form of a plurality of pairs of complementary bit lines (e.g., BIT, /BIT) that are electrically coupled to respective columns of memory cells within a memory cell array. Conventional techniques for switching data signals on pairs of complementary bit lines typically include using complementary drivers to actively pull one of the bit lines within a pair up from a logic 0 voltage to a full logic 1 voltage while simultaneously pulling the other bit line within the pair down from a logic 1 voltage to a logic 0 voltage. If the switching losses associated with the complementary drivers are ignored, then each switching event that causes BIT to switch low-to-high and /BIT to switch high-to-low, or vice versa, typically draws a charge of C(&Dgr;V
BIT
) coulombs from the power supply, where C represents the capacitance of a bit line and &Dgr;V
BIT
(or &Dgr;V
/BIT
) represents the voltage swing associated with pulling the true or complementary bit line from a logic 0 voltage to a logic 1 voltage. Assuming &Dgr;V
BIT
equals a power supply potential of Vdd, then the expression for charge required can be simplified to CVdd coulombs for each high-to-low and low-to-high switching event pair. A different expression may apply in the event the logic 0 voltage and the logic 1 voltage do not equal 0 volts and Vdd, respectively.
However, for many applications requiring reduced power consumption, including those having battery powered supplies and those in which total power consumption requires special heat dissipating packaging, the energy associated with drawing this charge from the power supply per switching event for each pair of data lines undergoing a data change is excessive. Accordingly, integrated circuit devices that can provide a full voltage swing across complementary data lines and have reduced power consumption requirements are desirable.
SUMMARY OF THE INVENTION
Memory devices and complementary data line driver circuits according to embodiments of the present invention conserve power by evaluating old data on complementary data lines and providing conditional charge recycling in the event the new data to be provided to the complementary data lines differs from the old data residing thereon. One preferred embodiment of a data line driver circuit includes first and second data lines within a complementary data line pair and a driver control circuit that is electrically coupled to the data line pair. The driver control circuit compares the old data on the data line pair to new data to be provided to the data line pair. Based on the comparison and a determination that the old data is opposite the new data, the driver control circuit switches the old data to the new data by first transferring charge from the more positively biased one of the first and second data lines to the other data line in the data line pair. The more positively biased one of the first and second data lines may initially be at a logic 1 voltage (e.g., Vdd) and the other data line in the pair may initially be at a logic 0 voltage (e.g., GND). After the charge transfer, both are approximately at ½ Vdd. In this manner, at least a portion of the total charge required to pull a data line from a logic 0 voltage to a logic 1 voltage (complementary data line from a logic 1 voltage to a logic 0 voltage) may be provided by an already charged (discharged) complementary data line (true data line), prior to actively pulling the data line high (complementary data line) low to complete the switching process.
According to a preferred aspect of this embodiment, the charge is transferred for a sufficient duration to substantially equilibrate voltages on the first and second data lines. In particular, if the first and second data lines are biased at Vdd and GND, respectively, the duration of the charge transfer may be sufficient to establish respective voltages in a neighborhood of about ½ Vdd on the first and second data lines. The first and second data lines are then driven with the new data at the completion of the power saving charge transfer. Alternatively, if the comparison results in a determination that the old data and the new data are the same, then the driver control circuit drives the first and second data lines with the old data and then the new data without interruption and without wasting power by transferring charge unnecessarily from the more positively biased one of the first and second data lines (retaining the old data) to the other data line in the data line pair.
According to another embodiment of the present invention, the driver control circuit may include a equalization transistor having a first current carrying terminal electrically coupled to the first data line and a second current carrying terminal electrically coupled to the second data line. This equalization transistor can provide a direct charge transfer path between the first and second data lines. The driver control circuit drives a gate of the equalization transistor with a turn-on voltage when charge is to be transferred and thereby recycled from one data line to the other in the pair. The driver control circuit may also include a latch that retains the old data while charge is being transferred from the more positively biased one of the first and second data lines. The driver control circuit may evaluate the old data retained by the latch against the new data when determining whether to initiate and continue charge transfer between the data lines. The old data on the latch is replaced with the new data only after the charge transfer process (if. required) is substantially complete. In particular, the operation of driving the first and second data lines from the midpoint to full rail-to-rail signal levels with the new data may be performed in-sync with switching the old data retained by the latch to the new data.
According to still a further aspect of this embodiment, the driver control circuit may include a true data line driver having a first output electrically connected to the first data line and a PMOS pull-up transistor therein. The PMOS pull-up transistor may have a drain electrically connected to the first output, a source electrically connected to a positive power supply line and a gate that receives a first active low signal equal to DATAINB+QB, where DATAIN and DATAINB are complementary signals that represent the new data, Q and QB are complementary signals that represent the old data retained by the latch, and “+” designates an OR operator. Accordingly, the PMOS pull-up transistor associated with the true data line driver will only be conductive (requiring the PMOS gate to be low) if the new data DATAIN=1 and the old data Q=1. A complementary data line driver is also provided that has a second output electrically connected to the second data line and a PMOS pull-up transistor having a drain electrically connected to the second output, a source electrically connected to the power supply line and a gate that receives a second signal equal to DATAIN+Q. Accordingly, the PMOS pull-up transistor associated with the complementary data line driver will only be conductive if the new data DATAIN=0 and the old data Q=0.
The true data line driver also includes a NMOS pull-down transistor having a drain electrically connected to the first output, a source electrically connected to a ground reference line and a gate that receives a signal equal to DATABIN×QB, where “x” designates an AND operator. Similarly, the complementary data line driver includes an NMOS pull-down transistor having a drain ele

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