Complementary code decoding by reduced sized circuits

Details Complementary code decoding by reduced sized circuits Complementary code decoding by reduced sized circuits

2007-02-27

2007-02-27

Ha, Dac V. (Department: 2611)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S142000, C375S150000, C708S422000

Reexamination Certificate

active

10464965

ABSTRACT:
A complementary code decoder technique is provided where the encoded input data is first parallelized. From the parallelized data, correlation values are generated by a correlator circuit that is capable of changing its correlation characteristics depending on at least one control signal. Different control signals are sequentially provided to the correlator circuit thereby driving the correlator circuit to sequentially generate multiple correlation values from the parallelized data, based on different correlation characteristics. From the multiple correlation values, the correlation value that represents the optimum correlation is identified. This technique significantly reduces the gate count of the decoder structure, thus saving chip area and manufacturing costs.

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patent: 6934319 (2005-08-01), Subramanian
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Heeg M: “Vernetzung Ohne Schnur, Neuer Chipsatz Beschleunigt Lokale Funknetze Auf 11 Mbit/s”, Elektronik, Franzis Verlag GMBH, Munchen, DE, vol. 48, No. 10, May 18, 1999, pp. 68-74, XP000896534 ISSN: 0013-5658.
International search report application No. PCT/US03/35434 mailed Apr. 28, 2004.

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