Semiconductor device manufacturing: process – Making regenerative-type switching device – Having field effect structure
Reexamination Certificate
2001-03-02
2003-01-07
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making regenerative-type switching device
Having field effect structure
C438S137000, C257S077000, C257S163000, C257S164000, C257S170000, C327S427000, C327S430000, C327S434000
Reexamination Certificate
active
06503782
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and system for fabricating integrated circuits, and in particular to a method and system for fabricating n-channel and p-channel junction field effect transistor circuits on a single wafer or die having pinchoff voltages of both positive and negative polarities.
2. Background of the Technology
The prior art for fabrication of silicon carbide (SiC) integrated circuits has consisted of two approaches to date, namely hybrid and monolithic. The hybrid approach includes mounting SiC metal-semiconductor field effect transistors (MESFETs) or junction field effect transistors (JFETs) onto a ceramic substrate, and wirebonding the bare die to traces that connect the other discrete components (e.g., resistors) to form the circuit. The advantage of this approach is that devices can be preselected for maximum performance, but assembly costs are high, and total circuit dimensions are large in comparison to the monolithic approach.
The existing monolithic approach in wide bandgap circuit design consists of standard complementary metal-oxide semiconductor (CMOS) circuit design using complementary logic via p-channel and n-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) integrated into the same chip. Complementary logic means that the gate bias needed to turn the devices on can be of either polarity. In silicon, CMOS is preferred for logic circuits owing to its low static power dissipation (due in part to its superior input impedance), and ease of logic circuit design, which is facilitated by the complementary performance that can be achieved between p-channel and n-channel devices. However, this approach, which is heavily used in silicon, ignores some basic problems with SiC and other wide bandgap systems. First, because of the wide bandgap, the barrier to leakage (via Fowler-Nordheim tunneling) currents through the oxide on SiC is dramatically reduced. This is especially true at higher temperatures, where SiC is projected for significant usage. Second, the reliability of the MOS system in silicon and SiC is suspect under extreme temperature and high radiation environments, which are both applications of great interest for SiC devices.
Third, the input impedance of a SiC JFET is significantly greater than that of a silicon JFET because of the difference in bandgap. Also, the JFET structure is more resistant than the MOSFET to damage or destruction as a result of electrostatic discharge or spikes in the input voltage signal. Finally, it is possible to fabricate complementary logic structures using SiC JFETs by varying the pinchoff voltage from negative to positive via channel thickness control. Although this is also possible in silicon JFETs, it is much more difficult to accomplish, and the voltage swing on the input of the device is much more restricted because the built-in potential of a silicon pn junction is a fraction of that in SiC. Exceeding the built-in potential of the gate-to-source pn junction will forward bias the junction and lead to excessive input leakage current through the gate terminal. This leakage current will dramatically degrade the device performance.
SUMMARY OF THE INVENTION
In order to overcome the problems with the prior art fabrication of SiC integrated circuits, as well as others, the present invention comprises a method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel JFETs on a single wafer or die, such that the produced devices are capable of having pinchoff voltages of either positive or negative polarities, including both types within the same circuit. In an embodiment of the present invention, a first layer of either p-type or n-type is formed as a base. An alternating channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one embodiment, pinchoff voltage is controlled via dopant level and thickness of the channel region. In another embodiment fabrication of devices occurs using a constant channel thickness, but with varied channel doping selectively across the wafer via implantation or selective epitaxial regrowth. In yet another embodiment of the present invention, both the doping and channel thickness of various devices in the circuit are selectively varied.
To achieve the stated and other advantages of the present invention, as embodied and described below, the invention includes a method for making integrated circuits having at least two junction field effect transistors, each of the at least two junction field effect transistors comprising a first layer, a second layer, and a third layer, each of the layers comprising a wide bandgap semiconductor material, the method comprising: providing a first heavily doped layer, the first heavily doped layer having a surface, and wherein the first heavily doped layer is a first type; forming a second layer on the surface of the first heavily doped layer, wherein the second layer has a thickness and a surface, and wherein the second layer is a second type; reducing the thickness of the second layer to predetermined thickness; and forming a third heavily doped layer of the first type on the surface of the second layer; wherein the predetermined thickness of the second layer for at least a first one of the at least two junction field effect transistors differs from the predetermined thickness of the second layer for at least a second one of the at least two junction field effect transistors.
To achieve the stated and other advantages of the present invention, as embodied and described below, the invention further includes a method for making integrated circuits having at least two junction field effect transistors, each of the at least two junction field effect transistors comprising a first layer, a second layer, and a third layer, each of the layers comprising a wide bandgap semiconductor material, the method comprising: providing a first heavily doped layer, the first heavily doped layer having a first layer surface, and wherein the first heavily doped layer is a first type; forming a second layer on the surface of the first heavily doped layer, wherein the second layer has a thickness, a surface, a breadth, and a doping, wherein the doping of the second layer varies across the breadth of the second layer, and wherein the second layer is a second type; reducing the thickness of the second type layer to predetermined thickness; and forming a third heavily doped layer of the first type on the surface of the second layer; wherein the doping of the second layer for at least a first one of the at least two junction field effect transistors differs from the doping of the second layer for at least a second one of the at least two junction field effect transistors.
To achieve the stated and other advantages of the present invention, as embodied and described below, the invention further includes a method for making an integrated circuit from layers using a wide bandgap semiconductor material, the circuit including at least two junction field effect transistors, comprising: providing a first heavily doped layer, the first heavily doped layer having a surface, wherein the first heavily doped layer comprises one selected from a group consisting of a p-type layer and an n-type layer, such that the first heavily doped layer has a first type; forming a second layer on the surface of the first heavily doped layer, wherein the second type layer has a surface and a thickness; wherein the second type differs from the first type; and wherein the second type is selected from a group consisting of a p-type layer and an n-type layer; variably reducing the second layer, such that the second layer has a varied thickness; and forming a third heavily doped layer of the first type on the surface of the second type layer, such that a first junction field effec
Blalock Benjamin
Casady Jeffrey Blaine
Mazzola Michael S.
Saddow Stephen E.
Berry Renee R
Kelber Steven B.
Mississippi State University Research and Technology Corporation
Nelms David
Piper Rudnick LLP
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