Complement reset latch

Details Complement reset latch Complement reset latch

2002-06-12

2003-06-10

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S212000

Reexamination Certificate

active

06577176

ABSTRACT:

RELATED APPLICATIONS
This application is related to the U.S. patent application of Robert Paul Masleid and Christophe Giacomotto, entitled “Complement Reset Buffer,” filed on even date herewith, the subject matter of which is incorporated by reference herein in its entirety.
FIELD OF THE INVENTION
This invention relates generally to logic latches and, more particularly, to storing the state of a signal along a long path in an integrated circuit or cross-chip interconnect.
BACKGROUND OF THE INVENTION
The operating speed of integrated circuits, such as microprocessors, is continually increasing. Typical high-speed integrated circuits have a clock cycle frequency greater than one gigahertz. In these devices, it is desirable to communicate data signals as quickly as possible. Buffers or repeaters are conventionally used along integrated circuit wire routes or in cross-chip interconnections to regenerate a degrading signal or to maintain fast transition times. As clock cycle frequency increases, clock cycle period becomes shorter, which makes it difficult for signals to propagate between circuit elements during one clock cycle period. Pipelining of a long wire or cross-chip interconnect is needed to preserve data integrity and meet timing constraints.
One conventional approach to pipelining long wire paths is to insert a standard latch in the wire path. This approach suffers, however, from poor performance. Typical latches have insertion delay and poor signal regeneration or signal driving characteristics. Regenerating the driving signal consumes further valuable time.
Another conventional technique is building a latch into an ordinary buffer. An ordinary buffer commonly includes two inverters in series. In a conventional CMOS design, the inverters are each formed from an NFET and a PFET transistor. Clock gating devices are commonly placed in series with the input NFET and input PFET devices. A problem with this technique is that adding clock gating devices along the critical path adds significant delay. Although faster than inserting a standard latch and regenerating the driving signal, this technique is expensive in chip area, clock power, and delay.
What is therefore needed is a repeater or buffer latch that is efficient as both as a buffer and as a data latch, does not have additional insertion delay, and consumes little clock power.
SUMMARY OF THE INVENTION
In an embodiment of the invention, a complement reset latch is integrated into a complement reset buffer. The complement reset latch performs efficiently as both a long wire signal repeater and a data latch. That is, a complement reset latch can be used both to regenerate a propagating signal and to hold an output signal at a stored value. Additionally, there is no latch insertion delay because the critical paths of the complement reset buffer are unaffected by the latch transistors. A state element is provided that does not add to the critical path or couple to critical path nodes. Further, the latch FETs are small devices that consume little power. This results in a clock load that is approximately 10 times smaller than a conventional repeater latch. A complement reset latch allows for efficient design of cross-chip paths, such as cache memory interfaces. Because a complement reset latch is built into a complement reset buffer, complement reset buffers can be easily replaced with complement reset latches where needed to meet timing constraints.
In another embodiment, a transparent complement reset latch is integrated in to a level-in-level-out buffer. A state element allows for input data to be selectively latched and held at the output node. Clock signals are used to control the state element and to gate the pulse generators of the buffer circuit. The pulse generators are enabled during transparent operation. However, when latched, the pulse generators are disabled to prevent the large FETs in the output stage from affecting the stored state.
In a further embodiment, a pulse complement reset latch is integrated into a level-in-level-out buffer. The pulse latch features a reconfigured critical path to optimize delay. The state output does not wait on data to change value as in the transparent embodiments. The pulse latch embodiment changes its output state in response to a clock pulse.
In a still further embodiment, a transparent complement reset latch is integrated in to a level-in-pulse-out buffer. While behaviorally similar to the transparent level-in-level-out latch, to provide a Q and Q′ pulse output, the output stage is modified to produce two separate state outputs Q and Q′.


REFERENCES:
patent: 5315173 (1994-05-01), Lee et al.
patent: 5576644 (1996-11-01), Pelella
patent: 6188259 (2001-02-01), Amir et al.
patent: 6222404 (2001-04-01), Mehta et al.

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