Compiling processing apparatus

Details Compiling processing apparatus Compiling processing apparatus

1996-05-30

1999-07-27

Hafiz, Tanq R.

395709, G06F 945

Patent

active

059305070

ABSTRACT:
A compiling processing apparatus which compiles a program operating in a computer having a cache memory. This apparatus collects memory access data for the cache memory, analyzes confliction relationships between them, determines whether or not an instruction for confliction memory access data relocates, relocates the instruction if relocation is possible, and reduces the number of cache miss. Further, this apparatus recognizes memory access data in a continuous area, audits recognized memory access data alignment, generates an instruction of pair-load/pair-store, and reduces the number of memory accesses.

REFERENCES:
patent: 5581762 (1996-12-01), Hayashi et al.
patent: 5613121 (1997-03-01), Blainey
patent: 5689712 (1997-11-01), Heisch
Lam, Monica S., et al., The Cache Performance and Optimizations of Blocked Algorithm, ASPLOS-IV Proceedings, pp. 63-75, Apr. 8, 1991.

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