Patent
1998-03-17
2000-03-14
Hafiz, Tariq R.
G06F 945
Patent
active
060383968
ABSTRACT:
A compiling apparatus and method, and a recording medium, are used to facilitate assembly code programming of a VLIW computer system. An instruction of an intermediate code format, designated for each slot of the VLIW instruction, is divided corresponding to each slot and stored into a plurality of intermediate code files. The instructions of the intermediate code format stored in the intermediate code files are then read in serially to execute an instruction scheduling process, taking into account dependency between instructions. The serialized instructions of the intermediate code format are converted into parallel assembly code, and an object program of the parallel assembly code is output.
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Hwang et al. Efficeint Code Generation for Digital Signal Processors with Parallel and Pipelined Instructions. IEEE. pp. 243-252, May 1997.
IBM Research:Basic Principles of VLIW Architectures, http://www.research.ibm.com/vliw/basic.html, Copyright 1995, jmoreno@watson.ibm.com (1 page).
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Asato Akira
Iwata Yasushi
Fujitsu Limited
Hafiz Tariq R.
Zhen Wei
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