Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Patent
1997-10-21
1999-12-07
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
395701, 395705, 712 1, 712 15, 712 28, 709200, 709201, G06F 945
Patent
active
059997346
ABSTRACT:
A distributed, compiler-oriented database is disclosed with operating modes including parallel compilation, parallel simulation and parallel execution of computer programs and hardware models. The invention utilizes a hardware apparatus consisting of shared memory multiprocessors, optionally augmented by processors with re-configurable logic execution pipelines or independently scheduled re-configurable logic blocks and a software database apparatus, manifest in the hardware apparatus, in order to efficiently support parallel database clients such as a source code analyzer, an elaborator, an optimizer, mapping and scheduling, code generation, linking/loading, execution/simulation, debugging, profiling, user interface and a file interface.
REFERENCES:
patent: 5088034 (1992-02-01), Ihara et al.
patent: 5111413 (1992-05-01), Lazansky et al.
patent: 5339429 (1994-08-01), Tanaka et al.
patent: 5361373 (1994-11-01), Gilson
patent: 5418953 (1995-05-01), Hunt et al.
patent: 5506999 (1996-04-01), Skillman et al.
patent: 5784636 (1998-07-01), Rupp
patent: 5841967 (1998-11-01), Sample et al.
J. Auslander et al., "Fast, Effective Dynamic Compilation", appears in Proceedings of PLDI '96, pp. 149-159, Pennsylvania, May 1996.
J-L. Baer et al., "Model, Design, and Evaluation of a Compiler for a Parallel Processing Environment", IEEE Transactions on Software Engineeing, vol. SE-3, No. 6, Nov. 1977.
Bernstein et al., "Distributed Compilation of VHDL", Vantage Analysis Systems, Inc., Spring 1992 VHDL International User's Group Meeting, May, 1992.
R. Chandra et al., "Data Distribution Support on Distributed Shared Memory Multiprocessors", appears in Proceeding of PLDI '97, pp. 334-345, Las Vegas, Nevada.
D. Engler, "VCODE: A Retargetable, Extensible, Very Fast Dynamic Code Generation System", appears in Proceeding of PLDI '96, pp. 160-170, Pennsylvania, May 1996.
K. Hering et al., "Hierarchical Strategy of Model partitioning for VLSI-Design Using an Improved Mixture of Experts Approach", 10.sup.th Workshop on Parallel and Distributed Simulation, (PADS '96), May 1996.
D. Skillicorn et al., "Parallel Compilation: A Status Report", External Technical Report, Queen's University, March 1990.
J. Willis, "Auriga: A Compiler that Addresses NUMA Architectures", WESCON/96 IC EXPO Applications Conference on Communications and Computer Technologies, Anaheim, CA, 1996.
J. willis et al., "MinSim: Optimized, Compiled VHDL Simulation Using Networked & Parallel Computers", appears in Proceedings of Fall 1993 VHDL International User's Forum.
J. Willis et al., "Optimizing VHDL Compilation for Parallel Simulation", IEEE Design & Test of Computers, Sep. 1992, pp. 42-53.
J. Willis, "Optimizing VHDL Compilation for Parallel Simulation", Carnegie Mellon University Dissertation, Pittsburgh, Pennsylvania, 1991.
Newshutz Robert Neill
Willis John Christopher
An Meng-Ai T.
El-Hady Nabil
FTL Systems, Inc.
Lervick Craig J.
LandOfFree
Compiler-oriented apparatus for parallel compilation, simulation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Compiler-oriented apparatus for parallel compilation, simulation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compiler-oriented apparatus for parallel compilation, simulation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-834147