Compiler and register allocation method

Data processing: software development – installation – and managem – Software program development tool – Translation of code

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C717S154000, C717S149000, C717S151000, C717S155000, C717S156000

Reexamination Certificate

active

09950904

ABSTRACT:
A computer, computer compiler and method for reducing the number of interferences between variables during graph coloring while maintaining the possibility that the instructions will be executed in parallel. A compiler, which converts into a machine language the source code of a program written in a programming language and optimizes the program includes: a directed acyclic graph DAG analysis unit11for constructing and analyzing a DAG for an instruction in a program to be processed; an interference graph construction unit12for employing the analysis results to construct an interference graph representing the probability that an interference will occur between variables used by the instructions; and a graph coloring unit13for allocating registers for the instruction based on the interference graph that is constructed.

REFERENCES:
patent: 4782444 (1988-11-01), Munshi et al.
patent: 5920716 (1999-07-01), Johnson et al.
patent: 6077313 (2000-06-01), Ruf
patent: 6260190 (2001-07-01), Ju
Koseki et al., A Register Allocation Technique Using Register Existence Graph, IEEE, 1997.
Koseki et al., A Register Allocation Technique Using Guarded PDG, ACM, 1996.
Norris et al., The Design and Implementation of RAP: A PDG-based Register Allocator, John Willey & Sons, 1998.
Proebsting et al., Probabilistic Register Allocation, ACM, 1992.
Traub et al., Quality and Speed in Linear-scan Register Allocation, ACM, 1998.
Kreahling et al., Profile Assisted Register Allocation, ACM, 2000.
Kurlander et al., Minimum Cost Interprocedural Register Allocation, ACM, 1996.
Kim et al., Unroll-Based Register Coalescing, ACM, 2000.
Makowski et al., Achieving Efficient Register Allocation Via Parallelism, ACM, 1995.
Callahan et al., Register Allocation via Hierarchical Graph Coloring, ACM, 1991.
Ferrante et al., The Program Dependence Graph and its Use in Optimization, ACM, 1987.
Norris et al., “Register allocation sensitive region scheduling,” 1995.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Compiler and register allocation method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Compiler and register allocation method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compiler and register allocation method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3840184

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.