Compiler and processor for processing loops at high speed

Details Compiler and processor for processing loops at high speed Compiler and processor for processing loops at high speed

1996-01-22

1998-12-15

Toplu, Lucien U.

395705, 395704, G06F 945

Patent

active

058505512

ABSTRACT:
A compiler comprises a loop detecting unit for extracting information of loops, and a high-speed loop applying unit generating a first loop exclusive instruction, placing the instruction immediately before the entry of a loop, generating second loop exclusive instructions, and placing the instruction at each place to branch to the entry of the loop. A processor comprises: a pipeline comprising: an instruction fetching unit, an instruction decoding unit, and an executing unit; a branch target storage unit; a branch target registering unit for, after the instruction decoding unit has decoded a first loop exclusive instruction, registering branch target information of an instruction succeeding to the first loop exclusive instruction in the branch target registering unit; and a branch executing unit for, after the decoding unit has decoded a second loop exclusive instruction, judging whether to execute a loop, if judges to execute, reading the branch target information registered in the branch target storage unit, and controlling the pipeline so that the program executes the loop using the read branch target information.

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John M. Feldman, Charles T. Retter, Computer Architecture A Designer's Text Based on Generic Risc, McGraw-Hill, Inc., Jan. 1994.

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