Compiler

Details Compiler Compiler

1999-03-31

2001-12-25

Powell, Mark R. (Department: 2122)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

Reexamination Certificate

active

06334212

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a compiler for translating a source program written in a high-level programming language into an object program written in a machine language.
In recent years, programmers have been trying very hard to improve the efficiency in developing a program by writing a program in a high-level programming language like C. The use of a high-level programming language enables a programmer to arbitrarily define a desired number of steps of holding, computing or transferring numerical values in a program using variables. That is to say, a programmer can freely write a program. During this process, a program written in such a high-level programming language (i.e., source program, which is also often called a “source code file”) should be compiled, or translated, by a compiler into an object program written in a computer-executable machine language (which is often called an “object code file”). The steps in the machine-executable object program are represented by machine instructions, which require registers or memories as operands. Accordingly, variables should be allocated to these registers or memories. Such allocation processing is called “resource allocation”. If optimum resource allocation has been performed successfully, then the code size of the object program can be minimized.
In general, allocating respective variables to registers turns out to be more advantageous in terms of code size and execution time rather than allocating them to memories. However, generally speaking, the number of available registers is relatively small. Thus, the degree of optimization achievable in the resource allocation solely depends on how efficiently variables can be allocated to register resources to execute a machine instruction using the registers as operands. In accordance with a conventional technique of optimizing resources allocation, a plurality of variables, allocable to the same register, are identified based on the respective ranges where the stored values of these variables are alive (in this specification, such a range will be called “variable life range”). Based on the results of this identification, the variables are allocated to the resources.
The present inventors proposed a data processor using the following two types of instruction formats and register models for the execution of instructions in Japanese Patent Application No. 10-59680.
FIGS. 10 through 20
outline the first instruction format.
In the first instruction format, a variable-length instruction with a minimum instruction length of 1 byte is described. A 2-bit field is used as a register-addressing field. Accordingly, four registers can be specified with one register-addressing field. In this architecture, four address registers and four data registers are defined. By separately using the address registers or the data registers responsive to a specific instruction, eight registers can be used in total in executing an instruction.
FIG. 10
illustrates a bit assignment for the first instruction format (
1
) in which a first instruction field composed of 1 byte, equal to the minimum instruction length, consists of an operation-specifying field and an arbitrary number of register-addressing fields. Specific examples of this format will be described below.
In an exemplary first instruction format (
1
)-(a), the first instruction field includes two 2-bit register-addressing fields and is composed of 1 byte, which is the minimum instruction length. And two operands can be specified in accordance with this format.
In another exemplary first instruction format (
1
)-(b), the first instruction field includes two 2-bit register-addressing fields, and an additional information field is further provided. Thus, the instruction length in accordance with this format is 2 bytes or more in total.
In still another exemplary first instruction format (
1
)-(c), the first instruction field includes one 2-bit register-addressing field and is composed of 1 byte, which is the minimum instruction length. And one operand can be specified in accordance with this format.
In yet another exemplary first instruction format (
1
)-(d), the first instruction field includes one 2-bit register-addressing field, and an additional information field is further provided. Thus, the instruction length in accordance with this format is 2 bytes or more in total.
In yet another exemplary first instruction format (
1
)-(e), the first instruction field includes no register-addressing fields and is composed of 1 byte, which is the minimum instruction length. Accordingly, in accordance with this format, no operands can be specified using addresses.
In yet another exemplary first instruction format (
1
)-(f), the first instruction field includes no register-addressing fields but an additional information field is further provided. Thus, the instruction length in accordance with this format is 2 bytes or more in total.
FIG. 11
illustrates part of a list of specific instructions for respective types of bit assignment shown in FIG.
10
. In
FIG. 11
, instruction mnemonics are shown on the left and the operations performed to execute these instructions are shown on the right.
FIG. 12
illustrates a bit assignment for a first instruction format (
2
) in which a first instruction field composed of 1 byte, i.e., the minimum instruction length, consists of an instruction-length-specifying field and a second instruction field consists of an operation-specifying field and an arbitrary number of register-addressing fields. Specific examples of this format will be described in detail below.
In an exemplary first instruction format (
2
)-(a), the second instruction field includes two 2-bit register-addressing fields and the first and second instruction fields are composed of 2 bytes. And two operands can be specified in accordance with this format.
In another exemplary first instruction format (
2
)-(b), the second instruction field includes two 2-bit register-addressing fields, and an additional information field is further provided. Thus, the instruction length in accordance with this format is 3 bytes or more in total.
In still another exemplary first instruction format (
2
)-(c), the second instruction field includes one 2-bit register-addressing field and the first and second instruction fields are composed of 2 bytes. And one operand can be specified in accordance with this format.
In yet another exemplary first instruction format (
2
)-(d), the second instruction field includes one 2-bit register-addressing field, and an additional information field is further provided. Thus, the instruction length in accordance with this format is 3 bytes or more in total.
In yet another exemplary first instruction format (
2
)-(e), the second instruction field includes no register-addressing fields and the first and second instruction fields are composed of 2 bytes. Accordingly, in accordance with this format, no operands can be specified using addresses.
In yet another exemplary first instruction format (
2
)-(f), the second instruction field includes no register-addressing fields but an additional information field is further provided. Thus, the instruction length in accordance with this format is 3 bytes or more in total.
FIG. 13
illustrates part of a list of specific instructions for respective types of bit assignment shown in FIG.
12
. In
FIG. 13
, instruction mnemonics are shown on the left and the operations performed to execute these instructions are shown on the right.
Accordingly, in accordance with the first instruction format shown in
FIGS. 10 through 13
, the instruction length of the first instruction field is used as a basic instruction length to specify a variable-length instruction. And an instruction can be described in this format to have a length N times as large as the basic instruction length and equal to or less than the maximum instruction length, which is M times as large as the basic instruction length (where N and M are both positive integers and 1≦N≦M). Since the minimum instruction length is

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