Compiled memory, ASIC chip, and layout method for compiled...

Details Compiled memory, ASIC chip, and layout method for compiled... Compiled memory, ASIC chip, and layout method for compiled...

2011-01-04

2011-01-04

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S185110, C365S230030

Reexamination Certificate

active

07864621

ABSTRACT:
Each of memory blocks includes word line groups each having at least one of word lines, memory cells and bit lines. A decoder unit selects couple control units corresponding to the memory blocks to be accessed, and decodes an address signal to select any of the word line groups. A logic of the decoder unit is formed by assigning a bit of the address signal to identify the memory blocks and the couple control units lower than a bit of the address signal to identify the word line groups. Accordingly, the numbers of word lines disposed at the memory blocks can be equalized with each other, and lengths of the bit lines can be shortened. As a result, a wiring delay of each of the bit lines can be minimized, and an access time of a compiled memory can be shortened.

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