Compilation for a SIMD RISC processor

Details Compilation for a SIMD RISC processor Compilation for a SIMD RISC processor

2005-11-29

2010-11-23

Bullock, Jr, Lewis A (Department: 2193)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C717S106000, C717S152000, C717S153000, C712S001000, C712S002000

Reexamination Certificate

active

07840954

ABSTRACT:
A computer implemented method, data processing system, and computer usable code are provided for generating code to perform scalar computations on a Single-Instruction Multiple-Data (SIMD) Reduced Instruction Set Computer (RISC) architecture. The illustrative embodiments generate code directed at loading at least one scalar value and generate code using at least one vector operation to generate a scalar result, wherein all scalar computation for integer and floating point data is performed in a SIMD vector execution unit.

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Eichenberger, Vectorization for SIMD Architectures with Alignment Constraints, May 2004, ACM SIGPLAN Notices, vol. 39, Issue 6, SESSION: Parellization, pp. 82-93.

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