Static information storage and retrieval – Read only systems – Semiconductive
Reexamination Certificate
2003-01-31
2003-07-29
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read only systems
Semiconductive
C365S103000, C365S094000, C365S189050
Reexamination Certificate
active
06600673
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention generally relates to read only memories (ROMs) and more particularly to using latches in register arrays as ROM cells for very small ROMs, where the ROMs are also selectively writeable.
2. Description of the Related Art
Conventional read only memories (ROMs) are formed using memory cells (such as transistors) permanently programmed using fuses or structural electrical connections. In addition, such ROM structures include built-in it self test (BIST) devices that are used to locate defective memory cells. The BIST devices have a minimum fixed size. For large memory arrays these BIST devices occupy a very small percentage (less than 5 percent) of the overall area of the ROM structure. However, if a very small ROM array (e.g., less than 2000 memory cells) were to be made, the BIST devices and peripheral support features could comprise a large percentage (more than 50%) of the total area. Therefore, there is a need to create a ROM array that does not require such BIST.
The invention described below provides a method and structure for forming ROMs smaller than a given threshold that do not require BIST or similar features by using non-conventional devices as memory cells and, in doing so, provides a ROM that is writeable.
SUMMARY OF INVENTION
The invention provides a pair of read only memory (ROM) cells having a first latch and a second latch. The first latch and the second latch are master and slave latches to one another. The first latch and the second latch include a write bitline connection that is permanently connected to a fixed voltage source (e.g., ground (
0
) or VDD (
1
)) to program the first latch and the second latch to permanent ROM values.
The first latch and the second latch further include read wordline connections, write wordline connections, read bitline connections and have a tri-state driver that has the read wordline connections and the read bitline connections. The read wordline connections are connected to a read wordline. The write wordline connections are connected to a write wordline. The read bitline connections are connected to read bitlines.
During read operations, the read bitlines are used to read the permanent ROM values. During initialization operations, the write wordlines are held active on all rows, to force the first latch and the second latch to the permanent ROM values. During test operations, after the initialization, data within the first latch or the second latch is scanned out. After a subsequent initialization, data in the other latch is scanned out.
The invention also provides a method for designing a read only memory (ROM) structure. The method entails inputting the number of ROM cells to be included in the structure. Next, the invention utilizes latches within a register array as the ROM cells if the number of ROM cells is below a threshold. The invention alters the design of the register array to permanently connect write bitline connections of the latches in the register array to ground or a voltage source to permanently program the latches. The altering of the design is such that, during initialization operations, write wordlines in the register array are held active on all rows, to force the latches to permanent ROM values. The invention also tests the design during test operations without a BIST. After the initialization, data within one latch of a pair of master/slave latches is scanned out and, after a subsequent initialization, the other latch of the pair is scanned out.
The invention provides a ROM array by modifying the register array (RA) of master/slave latches to permanently connect the write bitline connection to either ground or a set voltage value (VDD). By utilizing the register array with master/slave latches, the testing of the ROM array can be performed by a scan out operation, thereby eliminating the need for BIST. As noted above, it becomes impractical to design a conventional ROM array below a certain size because the relatively fixed size of the BIST devices becomes a larger and larger percentage of the overall device size, as the size of the array is decreased. To the contrary, with the inventive structure, the ROM array can be made as small as necessary, without incurring the area penalty associated with the relatively fixed size of the BIST, because the inventive structure performs testing using a scan out operation and avoids any such BIST structures.
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Croce Peter F.
Eustis Steven M.
Piro Ronald A.
Henkler, Esq. Richard A.
McGinn & Gibb PLLC
Tran Andrew Q.
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