Coded data generation or conversion – Sample and hold
Reexamination Certificate
2002-04-29
2003-07-22
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Sample and hold
C341S120000, C327S091000
Reexamination Certificate
active
06597299
ABSTRACT:
BACKGROUND OF THE INVENTION
Closed loop sample and hold circuits are often used in ADC (Analog-to-Digital Converter) circuits because of their high precision. In some cases, their precision is only limited by second-order effects related to switch non-linearities and buffer skewing. One notable drawback of using closed loop circuits in ADCs is their slow speed that results from the effects of feedback.
In contrast to closed loop circuits, open loop sample and hold circuits can be used in the fastest ADC circuits because of their ability to handle high speed signals (provide high input bandwidth) and reasonable power consumption. Open loop circuits typically employ at least one circuit in a feed-forward loop, in which non-linearities are not corrected by feedback. Thus, even though open loop circuits are fast, their use often results in additional circuit non-linearities that negatively impact the accuracy of a corresponding ADC device.
SUMMARY OF THE INVENTION
One aspect of the present invention is directed towards compensating open loop circuits in ADC devices. In an illustrative embodiment, a sample and hold circuit including a capacitor is charged to a sample voltage from an open loop circuit such as a transistor circuit controlled by an input voltage. The sample voltage on the capacitor is converted to a digital signal via an ADC (Analog to Digital Converter). A digital correction circuit compensates for differences in voltage between the sample voltage on the capacitor and the input voltage based on properties of the circuit and successive sample voltages on the capacitor. Consequently, nonlinearities can be corrected so that use of an open loop circuit or transistor circuit is less likely to negatively impact an overall accuracy of the ADC device.
In one application, the system for converting an analog input voltage includes multiple sample and hold circuits. For example, a first open loop sample and hold circuit can include a capacitor charged to a first sample voltage from a first transistor controlled by the input voltage. Additionally, a second open loop sample and hold circuit can include a capacitor charged to a second sample voltage from a second transistor also controlled by the input voltage. A digital correction circuit can compensate for non-linearities of at least one of the open loop circuits based on properties of the transistors and sample voltages on the capacitors at different times. More specifically, sample voltages on corresponding sample and hold circuits that track the input voltage can be converted at skewed sample times to compensate for non-linearities or device properties.
Each sample and hold circuit can include a current source to bias a transistor to produce a sample voltage on a corresponding capacitor. For example, an input voltage to be converted to a digital value can be applied to the base of a biased transistor. The output of the transistor, such as the emitter, can be coupled to charge the capacitor to a sample voltage. As discussed, the sample voltage on the capacitor can be fed to an ADC device for conversion.
A control circuit can be used to selectively couple the input voltage to the transistor and selectively activate a current source to bias the transistor. For example, the control circuit can control a switch that connects the input voltage to the transistor. Another switch can connect a current source to bias the transistor. Consequently, during a tracking mode, the input voltage can be coupled to the transistor to produce a sample voltage on the capacitor. During a hold mode, the capacitor stores the sample voltage and can be isolated from biasing and a potentially changing input voltage.
A digital correction circuit can correct for at least one non-linearity in an open loop circuit or transistor by accounting for an approximate current drawn by the capacitor as a result of a changing input voltage. One technique of correcting the non-linearities imparted by an open loop circuit is to approximate how much current is drawn by the capacitor during a charging period. Based on this information and other characteristics of the corresponding sample and hold circuit, the input voltage can be estimated.
In a specific application, the current drawn by the capacitor during a charge period can cause a voltage drop across the transistor depending on a changing input voltage. By calculating or approximating the current through the capacitor at the time of sampling, a corresponding portion of voltage drop between the input voltage and sample voltage caused by the current through the capacitor can be estimated. Accordingly, a precise value of the input voltage can be more accurately determined by compensating for the non-linearities of the open loop circuit.
The value of the input voltage at a particular time can be estimated using analog-to-digital conversions of sample voltages on the capacitor at two or more skewed sample times. For example, it is known that the sample voltage approximately tracks the input voltage as a consequence of the open loop circuit driving the capacitor. That is, the input voltage can drive an open loop gain circuit such as an emitter follower circuit to store a sample voltage on the capacitor. Values of multiple sample voltages on the capacitor can be used to identify how the input voltage changes over time. Based on how the sample voltage on the capacitor changes over time, the amount of current drawn by the capacitor and, hence, voltage drop across the transistor caused by a changing input voltage can be determined.
As previously discussed, multiple sample and hold circuits driven by a common input voltage can be implemented to accurately estimate the input voltage. A first sample voltage can be produced by a first open loop circuit and a second sample voltage can be produced by a second open loop circuit. A delay element to offset sample clocks of the first and second open loop circuits can be used to obtain corresponding time delayed sample voltages that are used to estimate an actual value of the input voltage.
The techniques according to the principles of the present invention are advantageous over the prior art. For example, an inherently fast open loop circuit such as a transistor in an emitter follower configuration can be used in a sample and hold circuit of an ADC device without foregoing overall converter accuracy.
REFERENCES:
patent: 5410269 (1995-04-01), Ohie et al.
patent: 5465093 (1995-11-01), Kusumoto et al.
patent: 5506525 (1996-04-01), Debroux
patent: 6081215 (2000-06-01), Kost et al.
patent: 6204794 (2001-03-01), Bult
patent: 6229354 (2001-05-01), Rapakko
patent: 6255979 (2001-07-01), Allee et al.
patent: 6340943 (2002-01-01), Chow et al.
patent: 6476647 (2002-11-01), Rapakko
Yoo, J., et al., “1-GSPS CMOS Flash Analog-to-Digital Converter for System-on-Chip Applications,” In Proc. IEEE Computer Society Workshop on VLSI, pp. 123-456 (Apr., 2001).
Yoo, J., et al., “Future-Ready Ultrafast 8bit CMOS ADC for System-on-Chip Applications,” In Proc. IEEE Int'l ASIC/SOC Conf., pp. 789-793 (Sep. 2001).
Engim, Inc.
Hamilton Brook Smith & Reynolds P.C.
Williams Howard L.
LandOfFree
Compensation techniques for electronic circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Compensation techniques for electronic circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compensation techniques for electronic circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3078005