Compensation of non-volatile memory chip non-idealities by...

Details Compensation of non-volatile memory chip non-idealities by... Compensation of non-volatile memory chip non-idealities by...

2011-07-12

2011-07-12

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240, C365S185290

Reexamination Certificate

active

07978520

ABSTRACT:
To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

REFERENCES:
patent: 6882567 (2005-04-01), Wong
patent: 6894931 (2005-05-01), Yaegashi
patent: 6937520 (2005-08-01), Ono
patent: 7020026 (2006-03-01), Guterman
patent: 7054193 (2006-05-01), Wong
patent: 7139192 (2006-11-01), Wong
patent: 2008/0316833 (2008-12-01), Fong et al.
patent: 0830684 (2004-08-01), None
patent: 0169604 (2001-09-01), None

Affiliated with

Also associated with

Rating

Compensation of non-volatile memory chip non-idealities by... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Compensation of non-volatile memory chip non-idealities by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compensation of non-volatile memory chip non-idealities by... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2636612