Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2002-07-12
2004-11-02
Pert, Evan (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S765010
Reexamination Certificate
active
06812691
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to an electronics device tester that transmits a test signal to multiple terminals of devices under test (DUTs), and in particular to a system for compensating for test signal degradation.
2. Description of Related Art
As illustrated in
FIGS. 1 and 2
, a prior art integrated circuit (IC) tester
10
tests a set of digital IC DUTs
12
before they are separated from the semiconductor wafer
16
on which they are formed by using an interconnect system
18
linking tester
10
to a set of probes
20
providing signal access to terminals
22
on the surfaces of the ICs. IC tester
10
includes a set of tester channels
14
, each capable of transmitting a digital test signal to an IC terminal or sampling a digital response signal produced at the IC terminal to determine its state. Interconnect system
18
includes a set of pogo pins
11
or other type of connectors for linking input/output terminals of each tester channel
14
to a probe board assembly
13
. Probe board assembly
13
includes one or more substrate layers containing conductive traces and vias forming signal paths between pogo pins
11
and probes
20
.
Since a semiconductor wafer
16
can hold a large number of ICs, and since each IC can have a large number of terminal pads, an IC tester
10
employing a separate channel to access each IC terminal would require a very large number of channels
14
to concurrently test all ICs on a wafer. Therefore an IC tester
10
usually tests only a portion of the ICs on a wafer
16
at the same time. Wafer
16
is typically mounted on a chuck
15
which positions wafer
16
so that probes
20
contact the terminals
22
of a particular set of ICs
12
to be tested. After tester
10
has tested that set of ICs
12
, chuck
15
repositions wafer
16
so that probes
20
contact terminals
22
of a next set of ICs to be tested.
To speed up the testing process, it is helpful to maximize the number of concurrently tested ICs
22
. As described in U.S. patent application Ser. No. 10/142,549 now pending entitled “Test Signal Distribution System for IC Tester, filed May 8, 2002”, incorporated herein by reference, one way to increase the number of ICs a tester can concurrently tests is to apply the test signal output of one channel to more than one IC input terminal. For example, when each IC to be tested is a random access memory (RAM) addressed by an 8-bit word, then each of a set of eight tester channels can concurrently send addresses to several RAMs, since all RAMs are to receive the same address sequence during the test.
Although interconnect system
18
provides paths for conveying signals in both directions between many tester channels
14
and IC terminals
22
,
FIG. 2
illustrates only a portion of one tester channel
14
linked by interconnect system
18
to several terminals
22
of ICs
12
on wafer
16
. A driver
24
, responding to control circuits (not shown) within channel
14
, generates an output signal of voltage V1. A resistance
26
of magnitude R1 links the driver's output signal V1 to a node
30
of interconnect system
18
to produce a test signal at node
30
of voltage V2. Resistance
26
includes the output resistance of driver
24
and any resistance in the path between the driver output and node
30
.
Interconnect system
18
distributes the test signal developed at node
30
to a set of probes
20
through a network of isolation resistors
28
, each of resistance R2. When made sufficiently large, isolation resistors
28
resistively isolate terminals
22
from one another to prevent a fault
32
to ground or to any other source of potential at the terminal
22
at any of one or more of ICs
12
from driving the other IC terminals
22
to the fault potential regardless of the voltage V1 at the output of driver
24
. Isolation resistors
28
enable tester
10
to test ICs
12
having no faults at their terminals when ICs receiving the same test signal do have faults at their terminals. Although
FIG. 2
shows isolation resistors
28
as forming a simple parallel network, as discussed in the previously mentioned U.S. patent application Ser. No. 10/142,549 now pending, resistors
28
may be arranged in other network topologies. Other nonlimiting examples are shown in U.S. patent application Ser. No. 09/613,531, filed Jul. 10, 2000 now pending.
The number of IC terminals
22
that a single tester channel
14
can drive is limited in part by the ability of driver
24
to maintain adequate test signal voltage at IC terminals
22
that are not experiencing faults when one or more other IC terminals
22
are experiencing faults. The input impedance at IC terminals
22
is primarily capacitive and they normally draw little steady state current after the test signal has had time to charge or discharge the IC terminal capacitance following a test signal state change. Thus under steady state conditions, the voltage appearing at each IC terminal
22
not experiencing a fault is substantially equal to V2. When driver
24
changes its output voltage V1 to a high or low logic level in response to a state change in an input “drive” control signal D, the test signal voltage V2 at node
30
at the junction of isolation resistors
28
rises or falls to steady state high or low logic voltage level that is substantially equal to V2 after the test signal current has fully charged or discharged the capacitance at IC terminals
22
. The slew of the test signal is a function of the IC terminal capacitance and of the resistances in the signal paths between driver
24
and terminals
22
.
When there is a fault
32
connecting the terminal
22
of one of ICs
12
, for example, to a source of low logic potential VL, then when driver
24
drives V1 from a low logic level VL to a high logic level VH, the voltage V2 at node
30
and at the terminals
22
not experiencing faults rise to
V
2=
VH−I*R
1
V
2=
VH−
(
VL−VH
)*
R
1/(
R
1+
R
2)
where I is the steady state fault current drawn by fault
32
. In a “worst case” situation, where driver
24
is connected to N+1 IC terminals
22
, N of those terminals could be linked by faults to a source of low logic level VL. In such case the steady state test signal voltage V2 at 30, and at the single remaining terminal
22
not experiencing a fault is
V
2=
VH
−(
VL−VH
)*
R
1/(
R
1+(
R
2
/N
)) [1]
Suppose faults link N of the N+1 terminals
22
to a source of high logic level VH at a time when driver
24
is pulling V1 to low logic level VL. In that case the steady state test signal voltage V2 at node
30
and at the single IC terminal
22
not subjected to a fault will be
V
2=
VL+
(
VH−VL
)*
R
1/(
R
1+(
R
2
/N
)) [2]
Equations [1] and [2] show that faults at any set of N IC terminals
22
can pull an IC terminal not subjected to faults above low logic level VL or below the high logic level VH in accordance with the ratio R1/(R1+(R2/N)). When faults pull the test signal voltage at terminals
22
too far above VL or to far below VH, the IC
12
having no fault at its terminal
22
will not recognize the logic state of the test signal and will therefore be untestable.
However the test system can be made fault tolerant when the resistance R2 of isolation resistors
28
is made sufficiently large. Equations [1] and [2] show that increasing the size of R2 reduces the influence of faults on test signal voltage on voltage V2 so that it can rise or fall closer to VH or VL. As the number N+1 of IC terminals
22
driven by the same test signal and the maximum number N of faults that must be tolerated increase, so too must the magnitude R2 of isolation resistors
28
in order to render the test system fault tolerant.
But increasing the magnitude of isolation resistance R2 reduces the rate at which driver
24
can charge or discharge the capacitance at IC terminals
22
when the t
FormFactor Inc.
Kobert Russell M.
Merkadeau Stuart L.
Pert Evan
Smith-Hill and Bedell PC
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