Compensation for amplifiers driving a capacitive load

Amplifiers – With semiconductor amplifying device – Including signal feedback means

Reexamination Certificate

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C330S267000

Reexamination Certificate

active

07825732

ABSTRACT:
This disclosure relates to load compensating multi-stage amplifier structures at an output of one of the amplifier stages.

REFERENCES:
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Desai, et al., “A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process”, 2007 IEEE International Solid-State Circuits Conference, pp. 308-309, 605, 462-463, and 615.
Lin, et al., “A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBQ in 0.18-μm CMOS”, IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 54, No. 2, Feb. 2007, pp. 131-135.
Peng, et al., “Transconductance with Capacitances Feedback Compensation for Multistage Amplifiers”, Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European Volume , Issue , Sep. 21-23, 2004, pp. 143-146.
Hernes, et al., “A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13μm CMOS”, 2007 IEEE International Solid-State Circuits Conference, pp. 462-463, 615.

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