Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-07-22
2002-10-08
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C147S019001, C147S019001, C147S007000, C331S00100A
Reexamination Certificate
active
06462593
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to electronic circuits, and, more particularly, to compensation circuits for phase-locked loops.
DESCRIPTION OF THE RELATED ART
The need to generate a local signal that is synchronized with an external reference signal is critical in many electronics applications such as frequency synthesis, clock recovery, clock generation and frequency demodulation. This coherence between the reference signal and the local replica is referred to as “phase synchronization”. This typically implies either that local signal either is in phase with the external reference signal or is offset from the reference signal by some phase constant.
At the heart of any such synchronization circuit is some form of a phase-locked loop circuit (PLL). Phase-locked loops are feedback control loops, whose controlled parameter is the phase of a locally generated replica of an incoming reference signal. Phase-locked loops have three basic components: a phase detector, a loop filter, and a voltage-controlled oscillator.
FIG.
1
—Basic PLL
A basic schematic diagram of a typical PLL
100
is presented in FIG.
1
. As shown, PLL
100
is configured to generate an output signal
126
in response to an input signal
110
. PLL
100
includes a phase detector
115
, a loop filter
120
, and a voltage-controlled oscillator (VCO)
125
. Phase detector
115
is coupled to receive input clock signal
110
and to produce output clock signal
126
. Phase detector
115
measures the phase difference between signals
110
and
126
(coupled here back to the phase detector
115
as feedback signal
127
), and generates a phase error signal
116
, which may be a voltage indicative of this phase difference. It is noted that the phase detector
115
illustrated in
FIG. 1
outputs a phase error signal
116
including an UP signal and a DN signal. The UP signal may be interpreted as indicating that the output signal
126
should be higher in frequency to match the input signal
110
. The DN signal may be interpreted as indicating that the output signal
126
should be lower in frequency to match the input signal
110
. In other embodiments, the phase error signal
116
may consist of a single signal or include more than two signals.
In some instances, phase detector
115
may also generate a phase error signal
116
even when there is no difference between signals
110
and
127
. For example, the phase detector
115
may output a small UP signal and a large DN signal, thereby providing both an UP signal and a DN signal to the filter
120
when only a DN signal may have been an appropriate signal of the phase error. As signals
110
and
127
change with respect to each other, signal
116
becomes a time-varying signal into loop filter
120
. This phase comparison is necessary to prevent output signal
126
from drifting with respect to reference signal
110
. As shown, the feedback signal
127
is an internal part of the PLL
100
. It is noted that the feedback signal
127
may be a signal external to the PLL
100
.
Loop filter
120
governs the response of PLL
100
to the error detected between signals
110
and
127
. A well-designed loop filter
116
should be able to track changes in the phase of the input signal
110
but should not be overly responsive to noise mixed with the input signal
110
. Loop filter
120
generates an error correction signal
121
, which is the input to VCO
125
. In one embodiment, a zero voltage on signal
121
causes the output of VCO
125
, output signal
126
, to oscillate at a predefined frequency, &ohgr;
0
, which is the “center” frequency of the oscillator. On the other hand, a positive voltage on error correction signal
121
causes output signal
126
to oscillate at a frequency which is greater than &ohgr;
0
. Conversely, a negative voltage on error correction signal
121
causes output signal
126
to oscillate at a frequency less than &ohgr;
0
.
In another embodiment, either only a positive voltage or only a negative voltage on error correction signal
121
is generated. In various embodiments, even when there is no difference between signals
110
and
127
, an error correction signal
121
is output. In still another embodiment, the error correction signal
121
is scaled such that although the error correction signal
121
is always of one sign, such as always positive, the error correction signal
121
corrects for oscillation either above or below the predefined frequency.
Generally speaking, in many embodiments, the output frequency of VCO
125
is a linear function of its input voltage over some range of input and output. “Phase lock” is achieved by feeding the output of VCO
125
back to phase detector
115
so that continual error correction may be performed. It is noted that PLL
100
may not achieve phase lock if input signal
110
is outside of some predetermined range.
In a simplest form, loop filter
120
is simply a conductor that receives a single phase error signal
116
from the phase detector
115
. In this simplest embodiment, the phase error
116
is equal to error correction signal
121
. Such a filter
120
allows PLL
100
to generate an output signal
126
which matches reference signal
110
in frequency and phase only if reference signal
110
is equal to the center frequency of VCO
125
. If reference signal
110
oscillates at a different frequency from the center frequency of VCO
125
, output signal
126
may match reference signal
110
in frequency but not phase. This “wire filter” is an example of a first-order PLL, which means that the denominator of the loop filter transfer function has no exponent value greater than one. In another embodiment of a first-order PLL, loop filter
120
includes an amplifier.
It is noted that PLL
100
may be fabricated on a monolithic substrate or produced from discrete components. The components
115
,
120
, and
125
used to create the PLL
100
may not be matched in electrical properties to each other, leading to instability of the PLL
100
. What is needed is a way to provide for an improved PLL circuit with greater stability.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a phase-locked loop circuit and method for providing for compensation for voltage offset. In one embodiment, a voltage offset between output signals of a phase detector may be reduced by a compensation circuit. The compensation circuit may advantageously allow for greater stability for the PLL, especially when the PLL is produced using discrete components.
A phase-locked loop circuit is contemplated comprising, in one embodiment, a phase detector, a compensation circuit, a loop filter, and a VCO. The phase detector is coupled to receive a first input signal and a second input signal. The phase detector is configured to output one or more of a plurality of output signals indicative of a difference between the first input signal and the second input signal. The compensation circuit is coupled to receive the output signals and to reduce a voltage offset between the output signals. The compensation circuit is further configured to provide a plurality of compensated output signals. The loop filter is coupled to receive the compensated control signals. The loop filter is configured to output a first control signal. The VCO is coupled to receive the first control signal and to output the second input signal based on the first control signal.
A method of operating a phase-locked loop circuit is also contemplated. In one embodiment, the method comprises receiving a first input signal and a second input signal. The method compares the first input signal and the second input signal and provides a plurality of output signals indicative of a result of comparing the first input signal and the second input signal. The method compensates for a voltage offset between the plurality of output signals to reduce the voltage offset. The method provides a plurality of compensated output signals indicative of the result of the compensating. The method filters the plurality of compensated contro
Doblar Drew G.
Wu Chung-Hsiao R.
Conley Rose & Tayon PC
Kivlin B. Noäl
Le Dinh T.
Sun Microsystems Inc.
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