Compensation circuit for leakage through electrostatic...

Details Compensation circuit for leakage through electrostatic... Compensation circuit for leakage through electrostatic...

2000-07-31

2003-04-29

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C327S198000

Reexamination Certificate

active

06556408

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of integrated circuits, and is more specifically directed toward reference voltage generation for mixed-signal integrated circuits.
Modern integrated circuits, as is well known, are fabricated using extremely small circuit elements. These small circuit elements, including both active devices such as transistors and also passive devices such as resistors and capacitors, have been observed to be quite vulnerable to damage from electrostatic discharge (ESD) events at their external terminals. As is well known, many ESD events are caused by a charged human touching a device's external terminal; accordingly, a conventional ESD test generates a charge corresponding to a “human body model”. Because of the small feature sizes in modern integrated circuits, a “killing” discharge can be caused by human contact at so low a voltage that the human is unaware of the discharge. Failure mechanisms caused by ESD events include shorted dielectric layers, such as transistor gate oxides, and conductors that are rendered open by excessive current density.
Because of this vulnerability, ESD protection circuits are now commonly implemented in modern integrated circuits. In general, ESD protection circuits are rapidly switching, high current capacity, switches, located in the integrated circuit at a point directly connected to external terminals. These devices are designed to provide a safe shunt for the transient currents of ESD events, sparing the high performance functional circuitry from the ESD energy. Examples of conventional ESD circuits include high threshold voltage transistors, drain extended MOS power transistors (referred to as “DENMOS” devices), thyristors, zener diodes, simple resistors, and combinations of these devices.
As is also well known in the art, the operation of many conventional analog or mixed-signal (i.e., both digital and analog) integrated circuits is based upon one or more reference voltages. Typically, the integrated circuit itself generates a regulated reference voltage based upon an externally applied power supply voltage. For proper operation, particularly in precise applications, the reference voltage must be well-regulated, and stable over variations in temperature, power supply voltage, and the like. Other reference levels can then be generated from this reference voltage.
In addition, as is fundamental in the art, device noise and the noise generated by an integrated circuit during its switching and other high frequency operation can couple to the generated reference voltage. As such, it is desirable to filter the reference voltage with a low-pass filter, preferably having a very low frequency pole (on the order of 10 Hz), so that any high frequency noise coupling to the reference voltage circuitry or output conductor does not affect the reference voltage itself. Such a low-pass filter is commonly implemented by way of a simple R-C network.
FIG. 1
illustrates a conventional mixed-signal integrated circuit incorporating a low-pass filter for its reference voltage. In this example, integrated circuit
2
includes reference voltage generation circuit
4
, which generates reference voltage V
ref
. In this example, a low-pass filter consists of resistor R
f
and capacitor C
oc
, which are connected in series between reference voltage V
ref
and ground, producing filtered reference voltage V
ref, filt
, which is applied to functional circuit
3
, which performs the desired digital and analog functions of the device, based upon reference voltage V
ref, filt
. The extremely low frequency pole that is desirable for the reference voltage V
ref, filt
requires the time constant corresponding to the product of the values of resistor R
f
and capacitor C
oc
to be quite large. Because of the premium placed upon integrated chip area, however, capacitor C
oc
cannot be efficiently implemented on-chip. Therefore, as shown in
FIG. 1
, capacitor C
oc
is typically implemented externally to the integrated circuit, as indicated in FIG.
1
. Resistor R
f
is preferably realized within integrated circuit
2
, as shown in FIG.
1
.
The external implementation of capacitor C
oc
of course requires an external terminal of integrated circuit
2
, to which one plate of capacitor C
oc
connects. As discussed above, however, each external terminal requires protection from ESD events, even if the terminal fails to carry a signal to any other external device or bus, as in the case of reference voltage V
ref
in integrated circuit
2
of FIG.
1
. Therefore, also as shown in
FIG. 1
, integrated circuit
2
includes ESD cell
6
, which is an ESD protection circuit realized on-chip with integrated circuit
2
, at the external terminal of reference voltage V
ref, filt
that is connected to capacitor C
oc
.
As is conventional in the art, ESD cell
6
is the source or sink of a non-zero leakage current I
leak
. Because integrated circuit
2
in this conventional example is a mixed-signal device, including digital circuitry and functionality, ESD cell
6
typically includes some type of MOS transistor, thus presenting a sub-threshold source-drain leakage to reference voltage V
ref
. Leakage current I
leak
from ESD cell
6
is significantly larger than that presented by analog-only ESD devices. For example, a typical leakage current I
leak
presented by ESD cell
6
may be on the order of 80 nA.
While this level of leakage is not detrimental to a digital function, or even to a signal input or output, this leakage will cause significant problems when present at the reference voltage V
ref
terminal of integrated circuit
2
. First, because of resistor R
f
in the low-pass filter, leakage current I
leak
will cause a voltage drop &Dgr;V across resistor R
f
. In portable applications such as wireless telephone handsets, where external component sizes (such as capacitor C
oc
) are kept to a minimum, resistor R
f
will have a relatively large value (e.g., 200 k&OHgr;) to provide the appropriate low-pass performance. As a result, voltage drop &Dgr;V can be quite sizable, e.g., a 17 mV drop for a 200 k&OHgr; and a 80 nA leakage current. This voltage drop &Dgr;V is not merely an offset to reference voltage V
ref
, however. Because MOS sub-threshold leakage current I
leak
is highly temperature sensitive, voltage drop &Dgr;V will vary significantly with temperature. As such, the voltage V
ref, filt
at the node between resistor R
f
and capacitor C
oc
will be quite uncertain over temperature. Because of the importance of an accurate reference voltage V
ref
in high-precision analog and mixed-signal circuits, the provision of ESD protection at the reference voltage terminal thus presents a severe limitation on the accuracy and precision of the functional circuitry.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide compensation for ESD cell leakage current at a reference voltage terminal of an integrated circuit.
It is a further object of the present invention to provide such compensation in a temperature-stable manner.
It is a further object of the present invention to provide such compensation as suitable for use in mixed-signal circuitry.
It is a further object of the present invention to provide such compensation for leakage current of either polarity.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented into an integrated circuit, such as a mixed-signal device or an analog circuit, having on-chip reference voltage generation capability that utilizes an external filter component for the reference voltage. A compensation circuit is connected in parallel with the ESD cell. The compensation circuit includes a dummy ESD cell that matches the ESD cell, and includes a current mirror that balances the

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