Compensation circuit for leakage in flash EPROM

Details Compensation circuit for leakage in flash EPROM Compensation circuit for leakage in flash EPROM

1990-11-19

1993-06-15

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

365218, G11C 1140

Patent

active

052205282

ABSTRACT:
An improvement in a memory array using single device floating gate flash memory cells for compensating for drain leakage. Drain leakage can cause hot hole injection during erasing thereby over-erasing a cell causing it to act as a depletion device. The column line is biased during erasing, raising the drain potential sufficiently high to prevent a leakage current path through the channel of the cell. A transistor is coupled to each column line and is selected during erase by a low potential to provide the bias for the drain regions.

REFERENCES:
patent: 4503524 (1985-03-01), McElroy
patent: 4888734 (1989-12-01), Lee et al.

Affiliated with

Also associated with

Rating

Compensation circuit for leakage in flash EPROM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Compensation circuit for leakage in flash EPROM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compensation circuit for leakage in flash EPROM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1048179