Compensation circuit for fractional-N frequency PLL synthesizer

Details Compensation circuit for fractional-N frequency PLL synthesizer Compensation circuit for fractional-N frequency PLL synthesizer

2001-02-02

2003-07-15

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C331S017000

Reexamination Certificate

active

06593783

ABSTRACT:

FIELD OF INVENTION
The present invention pertains to a frequency synthesizer. In particular, the present invention pertains to a frequency synthesizer that can correctly compensate for ripple current.
BACKGROUND OF THE INVENTION
Frequency-division multiple channel access systems are used in cellular telephones. In order to shift the transmission frequency to an empty channel, a frequency synthesizer capable of high-speed locking is required.
Reference numeral (
101
) in
FIG. 7
represents a conventional frequency synthesizer. A PLL (phase-locked loop) circuit of the fractional frequency-division type is used.
Said frequency synthesizer (
101
) is arranged in a semiconductor integrated circuit device which constitutes the sending/receiving circuit of a cellular phone. The frequency synthesizer comprises oscillator (
131
), frequency divider (
132
), reference clock signal generator (
133
), phase comparator (
134
), charge pump circuit (
135
), low-pass filter (
136
), compensation circuit (
137
), and control circuit (
138
). Oscillator (
131
) outputs an external output signal OUT. The external output signal OUT is input to frequency divider (
132
) and other circuits in the semiconductor integrated circuit device where said frequency synthesizer (
101
) is arranged.
Frequency divider (
132
) divides the frequency at the input external output signal OUT, generates a comparison signal; and then outputs the comparison signal. Said phase comparator (
134
) compares the phase of the comparison signal input from frequency divider (
132
) with the phase of the reference lock signal input from reference clock signal generator (
133
), controls charge pump circuit (
135
), and generates a control signal. The control signal is output to oscillator (
131
) via low-pass filter (
136
).
Oscillator (
131
) operates in such a way that the frequency of the external output signal OUT is varied according to the input control signal to make the phase of the comparison signal consistent with the phase of the reference clock signal. As a result, the frequency of the external output signal OUT becomes higher than the frequency of the reference clock signal by a multiple of the frequency division value of frequency divider (
132
).
Said frequency divider (
132
) is controlled by control circuit (
138
) so that its frequency division value varies periodically. For example, if the frequency of the reference clock signal is 200 kHz and the frequency division value is 5000 for seven clock cycles (35 &mgr;sec) and 5001 for one clock cycle (5 &mgr;sec), the average frequency division value obtained by averaging over eight clock cycles will be 5000.125 (=5000+⅛). The frequency of the external output signal OUT becomes 1000025 kHz, which is higher than the frequency of the reference clock signal by a multiple of the average frequency division value.
If the frequency division value is 4000 for six of eight cycles and is 4001 for the other two, the average frequency division value will be 4000.25, and the frequency of the external output signal OUT will be 800.050 MHz.
If the average frequency division value has a fractional part, it becomes possible to use a high frequency, such as 800 MHz or 1 GHz, in a narrow channel interval, such as 25 kHz or 12.5 kHz.
However, if the frequency division value is varied periodically as described above, even if after the external output signal OUT is locked to a desired frequency, a phase difference will occur due to inconsistency between the phase between the comparison signal and the reference clock signal. As a result, ripple current appears in the control signal output from charge pump circuit (
135
).
Reference symbol a in
FIG. 8
indicates the waveform of the comparison signal output from frequency divider (
132
) after the external output signal OUT is locked when the frequency division value is varied by N and N+1. Reference symbol b indicates the waveform of the reference clock signal. Reference symbol c indicates the waveform of the ripple current included in the control signal output from charge pump circuit (
135
) as a result of inconsistency between the phase of the comparison signal relative to the reference clock signal.
The ripple current included in the control circuit [sic; signal] will cause a spurious component to appear in the external output signal OUT. Therefore, the ripple current not only impairs the receiving performance of the cellular phone or another telecommunication device but also acts as a source of interference during communication. This is a very serious problem.
A compensation circuit (
137
) having D/A converter (
141
) and capacitor (
142
) is arranged in said frequency synthesizer (
101
). D/A converter (
141
) varies the voltage applied to capacitor (
142
) to generate a compensation current of opposite polarity and the same amount of charge as the ripple current. The compensation current is superimposed on the control signal output from charge pump circuit (
135
) to cancel the ripple current. As a result, an external output signal OUT without the spurious component is obtained.
The amount of charge in the ripple current varies with time in such a way that it is an integer multiple of a certain amount of unit charge. The amount of unit charge is the product of the phase difference between the comparison signal and reference clock signal and the output current of the charge pump circuit. In the example described above, the frequency of the external output signal OUT was 1000025 kHz; if the output current of charge pump circuit (
135
) is a constant current of +1 mA or −1 mA, the following Q
r
Q
r
=(⅛)×(1/1000025 kHz)×1 mA×½=62.5×10
−15
(Coulomb)  (101)
becomes the amount of unit charge.
The aforementioned compensation current with a charge amount in the range of ±1 time to a maximum of ±7 times (±Q
r
) the amount of unit charge Q
r
is generated with the same period as the reference clock signal in the sequence of
+7
Q
r
→+5
Q
r
→3
Q
r
→+1
Q
r
→−1
Q
r
→−3
Q
r
→−5
Q
r
→−7
Q
r
In order to compensate for the ripple current, with the capacitance of capacitor (
142
) taken as C
t
, if voltage V
e
which satisfies the following equation
C
t
·V
c
=Q
r
  (102)
is used as the unit and the output voltage is varied as −7V
e
, −5V
e
, −3V
e
, −1V
e
, +1V
e
, +3V
e
, +5V
e
, and +7V
e
by D/A converter (
141
), a compensation current with the opposite polarity and the same amount of charge as the ripple current can be generated.
However, as can be seen from said equation (101), the amount of the ripple current is proportional to the output current of charge pump circuit (
135
). Since the output current varies as a function of temperature, etc., the-ripple current cannot be compensated.
SUMMARY OF THE INVENTION
The general object of the present invention is to solve the aforementioned problems of the conventional technology by providing a technology which can correctly compensate for the ripple current.
This and other objects and features are provided by one aspect of the present invention by a frequency synthesizer comprising an oscillator that controls the frequency of an oscillation signal with an appropriate control signal, a frequency divider of the fractional frequency division type that frequency-divides the aforementioned oscillation signal and generates a comparison signal, a reference clock signal generator that generates a reference clock signal, a phase comparator that compares the phase of the aforementioned comparison signal with the phase of the aforementioned reference clock signal and outputs a phase difference signal, a charge pump circuit that outputs a current corresponding to the aforementioned phase difference signal, a low-pass filter that removes the high-frequency component of the current output from the aforementioned charge pump circuit and supplies

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