Compensation circuit for clock jitter compensation

Coded data generation or conversion – Converter calibration or testing

Reexamination Certificate

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Details

C341S144000

Reexamination Certificate

active

11451229

ABSTRACT:
A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an analogue output data signal comprising a jitter error due to said jitter, comprises a measurement circuit for measuring the jitter and a modelling circuit for generating a digital modelled jitter error signal which simulates the jitter error dependent on the measured jitter and the digital input data signal, wherein the digital modelled jitter error signal is subtracted from the digital input data signal.

REFERENCES:
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patent: 5576664 (1996-11-01), Herold et al.
patent: 5638010 (1997-06-01), Adams
patent: 6278394 (2001-08-01), May
patent: 6628711 (2003-09-01), Mathew et al.
patent: 6640193 (2003-10-01), Kuyel
patent: 7095819 (2006-08-01), Bellaouar et al.
patent: 7177430 (2007-02-01), Kim
German Office Action dated Mar. 13, 2006.

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