Compensation circuit and method for compensating for an offset

Pulse or digital communications – Receivers – Automatic baseline or threshold adjustment

Reexamination Certificate

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C375S219000, C375S222000, C375S317000

Reexamination Certificate

active

06823024

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a compensation circuit for an input signal having an offset and to a method for compensating for an offset in an input signal.
Digital modulation methods in telecommunication involve the amplitude, the frequency, or the phase of a signal that has a carrier frequency being modulated in accordance with a data string that is to be transmitted. Frequency modulation or frequency shift keying (FSK) involves keying between different frequencies. In the simplest case, there are two binary states—zero and one—accordingly, signal transmission requires only two frequencies disposed symmetrically around the carrier frequency.
In modern communication methods, such as Global System for Mobile Communication (GSM), a Gaussian Minimum Shift Keying (GMSK) method is used in which digital information is coded using Gaussian pulses instead of square-wave pulses. The GMSK method is a continuous-phase FSK method. Like GSM, the Digital Enhanced Cordless Telecommunication (DECT) method used for communication in cordless telephones is also an SSK method.
To demodulate a frequency-modulated signal in a demodulator, the carrier frequency is assigned a mid-voltage in the receiver. The output voltage from the demodulator in the receiver is higher than the intermediate voltage when a logic one is transmitted and is lower than the intermediate voltage when a logic zero is transmitted. In the frequency-modulated signal, the carrier frequency is increased by a particular frequency swing to transmit a one and is reduced by a particular frequency swing to transmit a zero.
Tolerances mean that the carrier frequency of the frequency-modulated signal can vary, for example, on account of temperature drifts in a transmitter. This means that the intermediate voltage associated with the carrier frequency can also vary at the output of the demodulator such that a DC voltage offset exists. Tolerances in the receiver or demodulator itself, for example, production-dependent or temperature-dependent tolerances, mean that the intermediate voltage is subject to additional fluctuations. To stipulate a decision threshold that distinguishes a voltage associated with a logic one from a voltage associated with a logic zero, and, hence, distinguishes between the two states, it is necessary to stipulate a threshold voltage that compensates for the intermediate voltage's DC voltage offset (DC offset).
In prior art communication systems, for example, in the case of the DECT standard, such a threshold voltage is stipulated by virtue of each user data block being preceded by a preamble with a string of 16 bits that alternately contains ones and zeros and is used for DC offset compensation. A simple low-pass filter can be used to ascertain the mean voltage value of such a signal train corresponding to the first 16 bits, and, at the end of the 16-bit preamble, the value so obtained can be stored, for example, as a voltage value on a capacitor. This averaging or the generation of a threshold voltage is normally controlled in the digital baseband chip of a DECT receiver.
The “Bluetooth” system describes a wireless interface between individual components of information and communication systems for data transmission over short distances. By way of example, peripheral devices such as printer, mouse, keyboard, mobile telephone, modem, etc. can be wirelessly connected to a portable computer. The Bluetooth system operates in the 2.4 gigahertz Industrial Scientific and Medical (ISM) band. In most of the world's countries, for example, USA and Europe, the ISM band covers the frequency range from 2,400 to 2,483.5 megahertz. In this case, the channels are defined using the formula f=2,402 +n MHz, where f is the carrier frequency of the channel in question and the variable n can assume integer values from 0 to 78.
The problem with the Bluetooth system, which operates using a time slot method, is that the preamble for an access code, which is respectively placed in front of the actual user signal (payload) and normally includes 72 bits, is only 4 bits long. In addition, this 4-bit preamble's position in time in a bit sequence can vary by up to 10 bits. However, this 4-bit preamble is too short to stipulate a suitable decision threshold for reliably distinguishing between the logic states.
It is a conventional practice to use digital signal processing to determine a decision threshold for the digitized and demodulated data signal in order to determine the switching threshold for Bluetooth. However, the circuits required for such determination are very complex and, depending on the implementation of the digital signal processing, unreliable. U.S. Pat. No. 4,821,292 to Childress discloses a detector circuit that changes over to a shorter time constant during a signal preamble for the purpose of averaging (dotting pattern). Such changeover achieves faster threshold-value readjustment.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a compensation circuit and method for compensating for an offset that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that are suitable for signals having a short preamble.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a compensation circuit for an input signal having an offset, including a filter unit receiving the input signal in a signal flow direction and having a signal path with a first time constant, a signal path with a second time constant, and a signal path with a third time constant, a first switch connected to the signal path with the first time constant and to the signal path with the second time constant for changing the filter unit between the signal path with the first time constant and the signal path with the second time constant, a second switch connected to the signal path with the third time constant for changing the filter unit over to the signal path with the third time constant, a first comparator connected downstream of the filter unit with respect to the signal flow direction, the first comparator having a first output, a second comparator connected downstream of the filter unit with respect to the signal flow direction, the second comparator having a second output, a third comparator connected downstream of the filter unit with respect to the signal flow direction, the third comparator having a third output, a first decoder connected to the first output and to the first switch for controlling the first switch, and a second decoder connected to the second switch and to a respective one of the second output and the third output for actuating the second switch.
With the objects of the invention in view, there is also provided a method for compensating for an offset in an input signal, including the steps of filtering an input signal utilizing a first time constant, forming an output signal having discrete states by comparing the filtered input signal with one of a threshold voltage and the input signal in unfiltered form, effecting a changeover to a second time constant longer than the first time constant in a setting mode if and for as long as the output signal has at least two identical, successive states, and setting the second time constant in a normal mode following the setting mode.
With the objects of the invention in view, there is also provided a method for compensating for an offset in an input signal, including the steps of generating a filtered output signal by filtering an input signal utilizing a first time constant, forming an output signal having discrete states by comparing the filtered output signal with one of a threshold voltage and the input signal in unfiltered form, effecting a changeover to a second time constant longer than the first time constant in a setting mode if and for as long as the output signal has at least two identical, successive states, and setting the second time constant in a normal mode following the settin

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