Compensating source voltage drop in non-volatile storage

Details Compensating source voltage drop in non-volatile storage Compensating source voltage drop in non-volatile storage

2007-04-24

2009-10-20

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180, C365S185220

Reexamination Certificate

active

07606071

ABSTRACT:
A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.

REFERENCES:
patent: 5386422 (1995-01-01), Endoh
patent: 5467306 (1995-11-01), Kaya
patent: 5522580 (1996-06-01), Varner, Jr.
patent: 5570315 (1996-10-01), Tanaka
patent: 5774397 (1998-06-01), Endoh
patent: 5838626 (1998-11-01), Nakayama
patent: 5923585 (1999-07-01), Wong
patent: 6046935 (2000-04-01), Takeuchi
patent: 6118702 (2000-09-01), Shieh
patent: 6125052 (2000-09-01), Tanaka
patent: 6166951 (2000-12-01), Derhocobian
patent: 6175522 (2001-01-01), Fang
patent: 6218895 (2001-04-01), De
patent: 6222762 (2001-04-01), Guterman
patent: 6272666 (2001-08-01), Borkar
patent: 6301155 (2001-10-01), Fujiwara
patent: 6456528 (2002-09-01), Chen
patent: 6484265 (2002-11-01), Borkar
patent: 6522580 (2003-02-01), Chen
patent: 6560152 (2003-05-01), Cernea
patent: 6608781 (2003-08-01), Jinbo et al.
patent: 6653890 (2003-11-01), Ono
patent: 6734490 (2004-05-01), Esseni
patent: 6771536 (2004-08-01), Li
patent: 6801454 (2004-10-01), Wang
patent: 6822905 (2004-11-01), Micheloni
patent: 6839281 (2005-01-01), Chen
patent: 6859397 (2005-02-01), Lutze
patent: 6870213 (2005-03-01), Cai
patent: 6882567 (2005-04-01), Wong
patent: 6900650 (2005-05-01), Sheng
patent: 6917237 (2005-07-01), Tschanz
patent: 6957163 (2005-10-01), Ando
patent: 7023736 (2006-04-01), Cernea
patent: 7046568 (2006-05-01), Cernea
patent: 7057958 (2006-06-01), So
patent: 7116588 (2006-10-01), Joo
patent: 7129771 (2006-10-01), Chen
patent: 7173854 (2007-02-01), Cernea
patent: 7196928 (2007-03-01), Chen
patent: 7196931 (2007-03-01), Cernea
patent: 7206230 (2007-04-01), Li
patent: 7334080 (2008-02-01), Takase
patent: 7468920 (2008-12-01), Sekar et al.
patent: 7508713 (2009-03-01), Sekar et al.
patent: 7525843 (2009-04-01), Sekar et al.
patent: 2002/0140496 (2002-10-01), Keshavarzi
patent: 2004/0057287 (2004-03-01), Cernea
patent: 2004/0109357 (2004-06-01), Cernea
patent: 2004/0255090 (2004-12-01), Guterman
patent: 2005/0024939 (2005-02-01), Chen
patent: 2005/0052219 (2005-03-01), Butler
patent: 2005/0111260 (2005-05-01), Nazarian
patent: 2005/0192773 (2005-09-01), Sheng
patent: 2006/0050562 (2006-03-01), Cernea
patent: 2006/0126390 (2006-06-01), Gorobets
patent: 2006/0140007 (2006-06-01), Cernea
patent: 2006/0158947 (2006-07-01), Chan
patent: 2006/0203545 (2006-09-01), Cernea
patent: 2006/0226889 (2006-10-01), Gupta
patent: 2006/0227613 (2006-10-01), Joo
Sekar, et al., U.S. Appl. No. 11/618,782, filed Dec. 30, 2006, titled Biasing Non-Volatile Storage to Compensate for Temperature Variations.
Sekar, et al., U.S. Appl. No. 11/618,786, filed Dec. 30, 2006, titled Non-Volatile Storage With Bias for Temperature Compensation.
Sekar, et al., U.S. Appl. No. 11/618,788, filed Dec. 30, 2006, titled Biasing Non-Volatile Storage Based on Selected Word Line.
Sekar, et al., U.S. Appl. No. 11/618,790, filed Dec. 30, 2006, titled Non-Volatile Storage With Bias Based On Selected Word Line.
Sekar, et al., U.S. Appl. No. 11/618,791, filed Dec. 30, 2006, titled Applying Adaptive Body Bias to Non-Volatile Storage.
Sekar, et al., U.S. Appl. No. 11/618,793, filed Dec. 30, 2006, titled Non-Volatile Storage With Adaptive Body Bias.
N. Shibata et al., A 70nm 16Gb 16-level-cell NAND Flash Memory, 2007 Symp. on VLSI Circuits Digest of Technical Papers, pp. 190-191, Jun. 14-16, 2007.
Y. Zhang et al., An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory, 2007 Symp. on VLSI Circuits Digest of Technical Papers, pp. 98-99, Jun. 14-16, 2007.
D.H. Kang et al., Novel Heat Dissipating Cell Scheme For Improving A Reset Distribution In A 512M Phase-Change Random Access Memory (PRAM), 2007 Symp. on VLSI Circuits Digest of Technical Papers, pp. 96-97, Jun. 14-16, 2007.
H. Tanaka et al., Bit Cost Scalable Technology With Punch And Plug Process For Ultra High Density Flash Memory, 2007 Symp. on VLSI Circuits Digest of Technical Papers, pp. 14-15, Jun. 14-16, 2007.
U.S. Appl. No., 11/739,509, filed Apr. 24, 2007.
Response to Office Action dated Jun. 24, 2009, U.S. Appl. No. 11/739,509, filed Apr. 24, 2007.
Office Action dated Jun. 10, 2009, U.S. Appl. No. 11/739,509, filed Apr. 24, 2007.

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