COMPENSATING CIRCUIT FOR USE IN A SWITCH CIRCUIT COMPRISING...

Details COMPENSATING CIRCUIT FOR USE IN A SWITCH CIRCUIT COMPRISING... COMPENSATING CIRCUIT FOR USE IN A SWITCH CIRCUIT COMPRISING...

2002-06-28

2004-06-08

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S120000, C341S136000, C341S143000

Reexamination Certificate

active

06747583

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to switch circuits comprising a plurality of scaled current steering switches which are selectively operable from one state to another in response to switching signals, and in particular, the invention relates to such a switch circuit in which time-skew resulting from failure of selected ones of the current steering switches to simultaneously switch from one state to the other in response to simultaneously applied switching signals is minimised. In particular, the invention relates to a compensating circuit for use with such a switch circuit for minimising time-skew. The invention also relates to a current steering digital to analogue converter (DAC) incorporating the compensating circuit. The invention also relates to a method for minimising time-skew in the selective switching of a plurality of scaled current steering switches from one state to another in response to respective simultaneously applied switching signals.
BACKGROUND OF THE INVENTION
In current steering DACs digital data is converted into an equivalent analogue output current which corresponds to the digital word being converted. The analogue current is derived from the sum of the currents from a plurality of binarily weighted current sources, which are weighted to correspond to the bits of the digital word from the least significant bit (LSB), to the most significant bit (MSB). In the conversion process the currents from the current sources corresponding to the bits of the digital word are steered into summing nodes, one node representing true data bits, and one node representing false data bits. The summing nodes are terminated with respective terminating resistors, and the summed currents are converted into output voltages developed across the respective terminating resistors.
It is important that non-linearities between the digital data inputted to such a DAC, and the analogue output be kept to a minimum. Such non-linearities originate from errors in the weighting ratios of the analogue currents, and from dynamic errors arising from the steering of the currents into the respective nodes in response to the digital data. In practical implementations of current steering DACs the currents from the current sources are switched to the summing nodes through current steering analogue switches, which in an integrated circuit are typically MOS transistor switches. The switches, in general, are provided as dual switch pairs, one dual switch pair being provided for each current source. The switches are scaled in size in proportion to the current to be switched from the corresponding current sources. The dual switch pairs are responsive to switching signals which are in turn responsive to the corresponding individual digital data bits. One of the switches of each dual switch pair is responsive to a true signal, and the other is responsive to a false signal. It is important that the “on” voltage across the switches for steering the currents from the current sources which is given by the following equation should be constant:
V
SW
=I
0
.2
i
.R
oni
=constant
where I
0
represents the current of the current source corresponding to the LSB,
i represents the bit, from bit i=0 (LSB) to bit i=n−1 (MSB), and
R
oni
represents the on resistance of the switch corresponding to bit i.
In MOS transistor switches the on resistance (R
on
) is inversely proportional to the geometric size of the switch, and thus from the above equation for the switch voltage V
SW
the MOS transistor switch for switching the current sources corresponding to the respective bit i must be of size 2
i
times the size of the MOS transistor switch for switching the LSB. Thus, in an n bit DAC each MOS switch of the dual switch pair for switching the current of the current source corresponding to the MSB must be of size 2
n−1
times the size of one of the MOS switches of the dual switch pair for switching the current source corresponding to the LSB, and so on for the switches of the dual switch pairs corresponding to the bits 2
n−2
, 2
n−3
, and so on.
The size of a MOS transistor switch is determined by the area of the switch, which in turn is determined by the length and width of the switch. The length is determined by the distance between the source and the drain of the switch, and the width is determined by the width of the source and drain, this will be well known to those skilled in the art.
The MOS current steering switches are switched in response to the respective corresponding bits of the digital data word. Respective driver circuits corresponding to the dual switch pairs output appropriate true and false switching signals in response to the digital data word for selectively switching the switches of the dual switch pairs. The switching signals are applied to the gates of the corresponding MOS switches of the dual switch pairs, for appropriately switching the switches. The switching load presented by a MOS switch to a corresponding driver circuit is a capacitive load, and is proportional to the switch size, and thus, the switching load presented to the driver circuits by the respective MOS switches are scaled in proportion to the scaling of the MOS switches. The capacitive switching load results from parasitic capacitance between the gate and the source and the gate and the drain, respectively, of the MOS switch, and also between the gate and the silicon of the MOS switch which is referred to as bulk capacitance.
Digital data samples are received by a DAC from a data register which is clocked at a constant rate, and thus, each digital data word is provided to the driver circuits simultaneously, and the switching signals, which are derived from the digital data word by the driver circuits are similarly provided by the driver circuits to the switches simultaneously. However, due to the fact that the switching loads presented to the respective driver circuits by their corresponding MOS switches differ due to the scaling of the switches, the switches are not simultaneously switched. This leads to time-skewing during switching of the MOS switches, which in turn leads to inter-symbol-interference and harmonic distortion. This type of distortion can become dominant for high data sampling rates which are common in DACs, and also in direct digital synthesisers.
Time-skew of the analogue output signal can be readily understood with reference to
FIG. 1
which illustrates the timing performance of a typical prior art n bit DAC. Waveform (A
LSB
) represents the output from the LSB register in response to a data word, and waveform (A
MSB
) represents the output of the MSB register in response to the data word. At time t
0
both A
LSB
and A
MSB
go high. Waveform B
LSB
represents the output voltage of the switching signal of the driver circuit of the MOS switch corresponding to the LSB, while waveform B
MSB
represents the output voltage of the switching signal of the driver circuit of the MOS switch corresponding to the MSB. Waveform C
LSB
represents the state of the MOS switch corresponding to the LSB, while waveform C
MSB
represents the state of the MOS switch corresponding to the MSB. Waveform D
LSB
represents the current I
0
flowing through the MOS switch corresponding to the LSB, while waveform D
MSB
represents the current flowing through the MOS switch corresponding to the MSB. The current waveform D
MSB
corresponding to the MSB which is I
0
.2
(n−1)
is not to scale.
At time t
0
the output from the LSB register and from the MSB register both go high simultaneously. Due to the capacitive switching load presented by the respective MOS switches corresponding to the LSB and the MSB to their corresponding driver circuits there is a time delay before the voltages of the switching signals from the driver circuits reach a level sufficient for switching the corresponding MOS switches. Due to the higher capacitive load presented by the MOS switch corresponding to the MSB than that presented by the MOS switch corresponding to the LSB, the time delay in

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