Compensated MOS timing network

Details Compensated MOS timing network Compensated MOS timing network

1978-02-07

1980-04-22

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307297, 307304, H03K 102, H03K 3353

Patent

active

041996933

ABSTRACT:
An MOS compensation circuit for stabilizing the discharge of a timing capacitor including first and second inverter circuits and an interconnecting feedback circuit which effectively compensate for impedance variances in a capacitor-discharging MOS transistor, particularly those impedance variances due to fabrication tolerance dependent parameters.

REFERENCES:
patent: 3673430 (1972-06-01), Donoghue
patent: 3806742 (1974-04-01), Powell
patent: 3823332 (1974-07-01), Feryszka et al.
patent: 3970875 (1976-07-01), Leehan
patent: 4004164 (1977-01-01), Cranford, Jr. et al.
patent: 4008406 (1977-02-01), Kawagoe
patent: 4016434 (1977-04-01), Defilippi
patent: 4049980 (1977-09-01), Maitland
patent: 4099264 (1978-07-01), Lodi
patent: 4128775 (1978-12-01), Frederiksen
Baitinger, "Constant-Current Source Network", IBM Tech. Disclosure Bull.; vol. 13, No. 9, p. 2516; 2/1971.
Chang, "FET N-Channel Threshold Voltage-Control Circuit", IBM Tech. Discl. Bull.; vol. 17, No. 1, p. 140; 6/1974.
Hummel, "Sentry Circuit for Substrate Voltage Control", IBM Tech. Discl. Bull., vol. 15, No. 2, pp. 478-479; 7/1972.

Affiliated with

Also associated with

Rating

Compensated MOS timing network does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Compensated MOS timing network, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compensated MOS timing network will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1476753