Compensated delay locked loop timing vernier

Details Compensated delay locked loop timing vernier Compensated delay locked loop timing vernier

1995-10-13

1997-11-04

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327158, 327236, 327270, 327284, H03K 513, H03K 526

Patent

active

056844212

ABSTRACT:
A timing vernier produces a set of timing signals of similar frequency and evenly distributed in phase by passing an input reference clock signal through a succession of delay stages, each stage providing a similar signal delay. A separate one of the timing signals is produced at the output of each delay stage. The reference clock signal and timing signal output of the last delay stage are supplied as inputs to a phase lock controller through separate adjustable first and second delay circuits. The phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock. In accordance with the invention, the delays of the first and second delay circuits are adjusted to compensate for controller phase lock error.

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Kim, B. Helman, D., and Gray, P.R., A 30MHz High-Speed Analog/Digital PLL in 2 Micron CMOS, pp. 1-13, published on or before Feb. 16, 1994.

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