Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-08-08
2002-07-23
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S107000, C438S128000, C438S617000
Reexamination Certificate
active
06423572
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of integrated circuits, in particular to integrated circuit packaging.
2. Description of Related Art
Programmable logic device (PLD) integrated circuits have facilitated the miniaturization of electronic devices by permitting a design engineer to replace a large number of specific-function logic ICs with a single IC without the high cost of fabricating a custom integrated circuit. Programmable logic devices are often structured internally as a large array of identical functional logic elements. The exact functioning of each logical element and the interconnections between them is programmed into the PLD before operation. The internal architectures of PLD's can vary but frequently a number of PLD's will share the same internal architecture and operating characteristics and be marketed as a family. The distinction between members in the family is the total number of functional logic elements included in each member.
It is not uncommon for a design engineer working with a PLD to use a member of a device family having a large number of functional logic elements. This guarantees that an adequate number of logic elements will be available and usually permits the engineer to generate and process additional signals at design time that are useful for testing and troubleshooting. When the design is completed a smaller member of the PLD family is selected for production use to reduce costs. Up until now, however, this meant redesigning the circuit board that holds the PLD device. Despite their common internal architecture that allowed migration between different packages in the family, their external packaging did not readily support migration. Consequently, there is a need in the art for integrated circuit packaging that ensures a migration path between related integrated circuits.
SUMMARY OF THE INVENTION
The present invention relates to integrated circuit packaging useful for programmable logic devices. The invention provides a migration path between a base integrated circuit and an extended integrated circuit that is a functional superset of the base. In the case of a programmable logic device (PLD), the pin element layout for a base integrated circuit provides for the connection of power, control, and I/O signals. Pins conducting power signals are located at the core of the base pin layout. Pins conducting control signals are located near the intersections of the horizontal and vertical axes of the layout and the perimeter of the layout. Remaining pins conduct I/O signals.
The pin element layout for an extended integrated circuit subsumes the base pin element layout. Additional pins for conducting power signals are located near one or more diagonal axes of the extended pin element layout. Methods for determining an extended integrated circuit pin element layout starting from a base pin element layout are disclosed.
Use of the invention can eliminate the need to create multiple circuit boards for related designs, such as development and production model designs, or entry-level and enhanced product designs. Embodiments employing the invention may also enjoy simpler and more reliable internal construction.
These and other purposes and advantages of the present invention will become more apparent to those skilled in the art from the following detailed description in conjunction with the appended drawings.
REFERENCES:
patent: 4990996 (1991-02-01), Kumar et al.
patent: 5036163 (1991-07-01), Spielberger et al.
patent: 5360767 (1994-11-01), Narrayanan et al.
patent: 5650660 (1997-07-01), Barrow
patent: 5703402 (1997-12-01), Chu et al.
patent: 5798571 (1998-08-01), Nakajima
patent: 5923540 (1999-07-01), Asada et al.
patent: 5952726 (1999-09-01), Liang
patent: 6033936 (2000-03-01), Tanaka
patent: 6057596 (2000-05-01), Lin et al.
patent: 6064113 (2000-05-01), Kirkman
patent: 6071755 (2000-06-01), Baba et al.
patent: 6101710 (2000-08-01), Selinger et al.
patent: 6107681 (2000-08-01), Lin
Texas Instruments, The MOS Memory Data Book, Texas Instruments Incorporated, Dallas, Texas, ICBN 0-89512-112-3, pp. 25-55 (1982).
Altera Corporation
Elms Richard
Morrison & Foerster / LLP
Pyonin Adam
LandOfFree
Compatible IC packages and methods for ensuring migration path does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Compatible IC packages and methods for ensuring migration path, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compatible IC packages and methods for ensuring migration path will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2843653