Comparison and verification system for logic circuits and method

Details Comparison and verification system for logic circuits and method Comparison and verification system for logic circuits and method

1990-08-07

1993-09-07

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1560

Patent

active

052435385

ABSTRACT:
When a hierarchy design is attempted in a logic design of a logic circuit, a system for verifying an equivalence between an upper level logic and a lower level logic is required. When the two different level logics are compared, the logics are once converted to Boolean expressions regardless of logic expressions of the logics, involving a logic circuit diagram and a truth table, and Shannon's formula is applied to the two Boolean expressions under a same order of variables to be extracted, to thereby produce binary decision diagrams (BDDs). When the equivalence between the produced BDDs is determined, the BDDs are simplified, respectively, and the simplified BDDs are integrated from the branches, and a determination can be carried out one time, i.e, without a repeat process.

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