Comparators

Details Comparators Comparators

1999-04-29

2002-07-16

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S065000, C327S072000

Reexamination Certificate

active

06420909

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits, and, more particularly, to a comparator.
BACKGROUND OF THE INVENTION
Comparator circuits are known and a typical. comparator circuit
1
is shown in FIG.
1
. The comparator circuit
1
shown in
FIG. 1
includes two pairs of transistors. The first and second transistors
2
and
4
are N channel field effect transistors (FETs) and defining the first pair of transistors. The first and second transistors
2
and
4
are matched. The source of each of the first and second transistors
2
and
4
is connected to ground. The gates of the first and second transistors
2
and
4
are connected to each other by a first line
6
. The drain of the first transistor
2
is connected to its gate.
The third and fourth transistors
14
and
18
are P channel FETs and define the second pair of transistors. The third and fourth transistors
14
and
18
are matched. The gate of the third transistor
14
is connected to a first voltage V
1
while the gate of the fourth transistor
18
is connected to a second voltage V
2
. The first and second voltages V
1
and V
2
are to be compared. One of the first and second voltages V
1
and V
2
may be a reference voltage. The drain of the third transistor
14
is connected to the drain of the first transistor
2
. The sources of the third and fourth transistors
14
and
18
are connected to a voltage supply Vcc or a current source.
The output of the comparator
1
is taken from an output node
20
which is between the drain of the fourth transistor
18
and the drain of the second transistor
4
. The output node
20
is connected to the input of an inverter
22
or any other additional gain stages yielding a logic output. The output of the inverter
22
represents the result of the comparison. If the output of the inverter
22
is high, then the first voltage V
1
is less than the second voltage V
2
. If the output of the inverter
22
is low, then the second voltage V
2
is less than the first voltage V
1
.
The operation of the circuit
1
shown in
FIG. 1
will now be described. The first and second voltages V
1
and V
2
are applied to the respective gates of the third and fourth transistors
14
and
18
. The size of the voltage applied to the gates of the third and fourth transistors
14
and
18
will determine how quickly these transistors are turned on. The lower the voltage applied to the gate of the third or fourth transistor
14
or
18
, the more quickly that transistor will be turned on. If the first voltage V
1
is less than the second voltage V
2
, the third transistor
14
will be turned on more quickly than the fourth transistor
18
. If the third transistor
14
is on, the drain voltage of the first transistor
2
and the gate voltages of the first and second transistors
2
and
4
will depend on how quickly the third transistor is turned on. The more quickly the third transistor
14
is turned on, the higher the voltage applied to the gates of the first and second transistors
2
and
4
and the more quickly the first and second transistors
2
and
4
are turned on. The voltage at the output node
20
will tend to be pulled low if the second transistor
4
is relatively quickly switched on in comparison to the first transistor
18
. Thus, the output of the inverter
22
will be high.
If the second voltage V
2
is less than the first voltage V
1
, the fourth transistor
18
will be switched on more quickly than the third transistor
14
. If the third transistor
14
is switched on relatively slow, a lower gate voltage will be applied to the first and second transistors
2
and
4
. This in turn means that the first and second transistors will be relatively slowly turned on. As the second transistor
4
is relatively slowly turned on and the fourth transistor
18
is relatively quickly turned on, the output node
20
will tend to be pulled up so that the voltage at this node will be high. Accordingly, the input to the inverter
22
will be high and thus the output of the inverter
22
will be low.
One well known use of comparators is in a Schmitt trigger. A typical Schmitt trigger is shown in FIG.
2
. The principal behind a Schmitt trigger will be described in relation to
FIG. 3
which shows how two voltages Vinp and Vinn vary with time. For simplicity, Vinn is a constant voltage whereas Vinp varies with time.
FIG. 3
also shows the associated set and reset signals produced by the Schmitt trigger.
The Schmitt trigger is arranged to provide a set (or reset) signal each time Vinp exceeds the value of Vinn by a certain value. The Schmitt trigger provides a set signal in the example shown in
FIG. 3
when Vinp exceeds Vinn by a value equal to Vthreshold
1
. Likewise, a reset (or set) signal is provided when Vinp is less than Vinn by a predetermined amount. In the example, the reset (or set) signal is provided when Vinp is less than Vinn by a value equal to Vthreshold
2
. The use of threshold values Vthreshold
1
and Vthreshold
2
means that it is less likely that a noisy input voltage would produce false set and/or reset signals.
FIG. 2
shows a Schmitt trigger which operates in accordance with the principals shown in FIG.
3
. The Schmitt trigger includes two comparator circuits
1
of the type shown in FIG.
1
. Additionally, the positive input of each comparator circuit
1
can be regarded as having a voltage source
13
and
15
respectively connected to the input. These voltage sources
13
and
15
determine the threshold value Vthreshold
1
and Vthreshold
2
. Typically, these voltage sources
13
and
15
will take the form of a feedback circuit which connects the output of the comparator
1
to its input.
Typically a high input impedance differential Schmitt trigger requires a pair of controlled offset buffers to form these voltage sources
13
and
15
. If the high input impedance or differential inputs were not required, a Schmitt trigger can be formed using a single comparator and a resistive positive feedback network.
SUMMARY OF THE INVENTION
An object of the present invention to provide a comparator which avoids or reduces the problems of the known arrangements as discussed above.
According to one aspect of the present invention, a circuit for comparing a first voltage and a second voltage includes a comparator having a current divider for dividing a bias current in accordance with the values of the first and second voltages, and for providing two currents. A current differentiation circuit receives the currents and provides an output dependent upon the difference between the currents. At least one of the current divider and current differentiation circuits weights one of the currents with respect to the other so that a given output signal is only provided when the difference between the first and second voltages exceeds an offset value. A bias generator includes a second comparator in the same configuration having the same components as the other comparator.
In this way, a comparator with an offset voltage can be provided without the need to provide the additional elements required, for example, to implement the Schmitt trigger of FIG.
2
. Preferably, at least one of the current divider and current differentiation circuits includes a pair of transistors. At least one pair of transistors may not be matched to weight one of currents with respect to the other. The current differentiation circuit may include a current mirror.
Preferably the current divider includes a first pair of transistors of a first polarity or channel type, and the current differentiation circuit includes a second pair of transistors of a second polarity. Each transistor of each pair includes first and second current path terminals and a control terminal. The control terminals of the first pair of transistors are arranged to receive the first and second voltages respectively. One of the current path terminals of each of the first pair of transistors are arranged to be connected to receive a part of the biasing current, and the other of the current path terminals of the first

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