Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-08-16
2003-07-22
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000
Reexamination Certificate
active
06597303
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to comparator circuits. More particularly, it relates to a comparator having a latching circuit, in which the coupling of the input signal into the latch and/or the coupling of the output signal from the latch are designed to minimize the internal loading of the latch. The reduced loading allows this comparator circuit, when it is switched from acquisition (or tracking) mode to latching (or regenerative) mode, to resolve a very small input difference into a full logic level more rapidly than any previously known comparator circuit implemented with a given transistor technology.
A latching comparator determines, at a particular instant, which of two voltages is larger, or equivalently, determines the sign of a voltage difference. The output of the comparator is generally a logic voltage level compatible with the inputs of some particular logic circuitry. If the voltage difference to be resolved is small compared to the logic voltage swing, some period of time is required after the comparator is clocked for the voltage to be amplified to a recognizable logic level. A small input voltage difference generally begins to grow at an exponential rate, characterized by a so-called “regeneration time constant”, when the comparator clock signal is switched. The smallest voltage difference that can be resolved by the comparator in a given period of time is limited by the value of this constant. This means that if an input difference is too small it will not produce a valid logic signal in the allotted time interval.
2. Description of the Related Art
The best regeneration time for prior art comparator circuits is achieved with a differential current-mode latch with the input and output coupled into taps in the collector load resistors of the latch. See, for instance, R. Van de Plassche,
Integrated Analog
-
to
-
Digital and Digital
-
to
-
Analog Converters,
Klever Academic Publishers, 1994, pp. 121-122. However, the input transistor collectors and output transistor bases still significantly load the latch.
In the usual prior art implementation of a clocked latching comparator, a clock signal switches the comparator between an acquisition mode and a latching mode. In the acquisition mode the comparator has a relatively low gain and the output follows the signal input. When the comparator is clocked into the latching mode, positive feedback is enabled so that any arbitrarily small signal that is present will regenerate and drive the latch to its full output swing. When the signal is small, the rate of growth is proportional to the signal voltage present at any given time. This means that the regeneration is characteristically exponential in time, with a regeneration time constant T
r
. If the clock timing for the comparator allows some time T for regeneration, the input signal should be at least exp(−T/T
r
)·V
sw
to be resolved, where V
sw
is the value of a full logic swing. Smaller inputs will not be able to reach a full logic swing and may not be correctly resolved by the subsequent logic. This undesired condition is referred to as comparator (or latch) metastability.
The regeneration time constant for a comparator (or, in general, any latch) is determined primarily by the gain in the positive feedback loop and by the loading of various capacitances in the circuit.
FIG. 1
shows a simplified electrical circuit of a prior art differential current-mode latch. An example of this circuit can be for example found in U.S. Pat. No. 4,083,043 to D. R. Breuer and in D. R. Breuer, ‘High-speed A/D Converter Monolithic Techniques’, International Solid State Circuits Conference Proceedings, February 1972, pp. 146-147 and 228.
The circuit of
FIG. 1
comprises an input differential pair of transistors Q
1
-Q
2
, a latch differential pair of transistors Q
3
-Q
4
, a clock differential pair of transistors Q
5
-Q
6
, load resistors R
1
and R
2
and a current source I
1
. The clock differential pair Q
5
-Q
6
steers the current from the current source I
1
into either the input differential pair Q
1
-Q
2
when the clock input signal CLK is high, or into the latch differential pair Q
3
-Q
4
when the clock signal CLKX is high. CLK and CLKX are complementary signals; when one is low the other is high and vice versa.
When the clock signal CLK is high, the input differential pair Q
1
-Q
2
operates as a transconductor which converts the input voltage difference at the bases of Q
1
and Q
2
to a difference in the collector currents of Q
1
and Q
2
. The collector currents flow into the high impedance of the load resistors R
1
and R
2
at the nodes A and B of FIG.
1
and create a voltage difference between these nodes which is an amplified replica of the input voltage difference at the bases of Q
1
and Q
2
.
When the differential clock voltage is switched so that CLK goes low and CLKX goes high, the input pair Q
1
-Q
2
is deactivated and the latch pair Q
3
-Q
4
becomes active. The latch pair Q
3
-Q
4
and the load resistors R
1
and R
2
form a very high gain positive-feedback amplifier such that any voltage present between A and B will be amplified (or “regenerated”) until the latch is driven to a saturated output. The output of the comparator may be taken either directly from A and B as shown in
FIG. 1
or through some sort of buffer amplifier that has its inputs connected to A and B.
To use this circuit as a strobed comparator, the voltage difference to be compared is applied between the input signals IN and INX while the clock signal CLK is high. At the time the comparison is to be made, the clock signal CLKX is rapidly switched high so that the amplified input voltage differential serves as the starting point for the latch to regenerate to a saturated output level. The rate of regeneration depends inversely on the capacitive loading at the high impedance nodes A and B. In a conventional integrated circuit implementation of the comparator, this loading essentially consists of:
a) collector-base and base-emitter capacitances of Q
3
and Q
4
;
b) parasitic collector-substrate capacitances of Q
3
and Q
4
;
c) substrate capacitance of the resistors R
1
and R
2
;
d) collector-base capacitance of Q
1
and Q
2
;
e) parasitic collector-substrate capacitances of Q
1
and Q
2
; and
f) the output load, which is usually at least the collector-base and base-emitter capacitances of emitter followers or of a differential pair.
Items a, b, and c above are inherently part of the regenerative latch, whereas items d, e, and f are associated with the circuitry used to couple signals into and out of the latch.
In order to use this circuit as a high speed latching comparator and to reduce the loading due to the above circumstances, various modifications have been made up to now. These modifications have included in particular the use of emitter followers in the latch, and a split collector load resistor. These modifications have provided a higher loop gain in the latch, a higher collector-base voltage for Q
3
and Q
4
, together with some degree of isolation of the capacitances of the input pair, Q
1
and Q
2
, and of the output load from the loop involving Q
3
and Q
4
when the regeneration takes place. However, also when taking into account all of these modifications, the value of the regeneration time constant has always been limited to some degree by the above loadings.
SUMMARY OF THE INVENTION
The present invention solves the aforementioned prior art problems by providing a comparator, having a comparator input receiving a first input signal and a second input signal during an acquisition mode, and having a comparator output outputting a comparator output signal indicative of the largest between the first input signal and the second input signal, the comparator comprising: a cross-coupled regenerative latch for regenerating, during a latching mode, a signal which is indicative of a difference between the first input signal and the second input signal; a circuit connected to the cross-coupled regenerative latch, operating a
HRL Laboratories LLC
Jeanglaude Jean Bruner
Ladas & Parry
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