Comparator with jitter mitigation

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude

Reexamination Certificate

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Reexamination Certificate

active

08040159

ABSTRACT:
In one example, a comparator circuit includes a differential stage adapted to receive a differential input signal. The comparator circuit includes first and second diodes coupled to the differential stage. The first and second diodes are adapted to selectively switch on and off to provide a differential output signal at first and second differential output nodes in response to the differential input signal. The comparator circuit includes a current steering circuit adapted to selectively provide a reference current from a current source to the first or second diode in an off state to reduce a voltage swing of the first or second diode between the off state and an on state. The comparator circuit includes an output stage coupled to the first and second diodes at the first and second differential output nodes. The output stage is adapted to convert the differential output signal to a single ended output signal.

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Tyhack et al., IEEE Journal of Solid-State Circuits, A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface, vol. 40, No. 9, Sep. 2005, pp. 1829-1838.

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