Comparator offset calibration for A/D converters

Details Comparator offset calibration for A/D converters Comparator offset calibration for A/D converters

2006-07-11

2006-07-11

Barnie, Rexford (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S118000

Reexamination Certificate

active

07075465

ABSTRACT:
An A/D converter includes at least one comparator array (COMP1–COMP7) for flash A/D conversion of an analog signal. Means (CCU, SW1–SW7) provide, for each comparator in the array, a common reference signal to both comparator input terminals. Means (CCU, DAC1–DAC7) force each compara-tor in the array into the same logical output state. Finally, means (CCU, DAC1–DAC7) adjust the comparator trip-point for each comparator by a ramp signal until the logical output state is inverted.

REFERENCES:
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patent: 6205078 (2001-03-01), Merritt
patent: 6320426 (2001-11-01), Shih
patent: 6496129 (2002-12-01), Dedic et al.
patent: 6515464 (2003-02-01), Darmawaskita et al.
patent: 6720757 (2004-04-01), Khorram et al.
patent: WO 02069502 (2002-09-01), None
patent: WO 02082660 (2002-10-01), None
Swedish Patent Office, International Search Report for PCT/SE03/00297, dated May 30, 2003.

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