Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-02-25
2001-10-16
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S065000
Reexamination Certificate
active
06304107
ABSTRACT:
BACKGROUND OF THE INVENTION
Comparators are often employed in connection with devices such as data converters, control systems and feedback loops. Generally, detection circuitry is provided between a comparator and downstream circuitry. Hence, the comparator drives the inputs of the detection circuitry. Oftentimes, the circuitry which is downstream from the detection circuitry and receives the output of the detection circuitry is digital. For optimum performance, it is important for a detection circuit to be configured to quickly and consistently supply a single, definite output to the downstream circuitry. If the circuit fails to provide a stable output to downstream circuitry, data conversion speed and accuracy, for example, may suffer.
Normally, a comparator drives the inputs of a detection circuit to the supply rails, wherein the supply rails comprise the power supply to the detection circuit. Comparator metastability occurs when a comparator is not able to achieve a definite decision level for the downstream circuitry. Metastability may occur when the outputs of a comparator are balanced between the supply rails. A metastable condition may also occur if a differential between the outputs of the comparator (the inputs of the detection circuit) is too small. In such a case, the detection circuit may take too much time to attain a decision level. Another common metastable condition is when the comparator attains multiple decision levels within a single clock cycle, thereby confusing downstream circuitry.
The advantages of avoiding a metastability condition include, but are not limited to: improved data conversion speed and accuracy (i.e., lower Bit Error Rate (BER)), allowing new applications for older or generally unconventional circuit topologies, providing smaller comparator gain stages, providing less comparator gain stages, providing that control loops are more stable and providing that control loops have higher bandwidths.
OBJECTS AND SUMMARY
It is an object of an embodiment of the present invention to provide a detection circuit which provides improved metastability performance.
It is a further object of an embodiment of the present invention to provide a detection circuit which provides a high common mode rejection ratio and high common mode input range.
It is a further object of an embodiment of the present invention to provide a detection circuit which provides a large input hysteresis range that improves metastability rejection.
It is a further object of an embodiment of the present invention to provide a detection circuit which reduces the amount of time required to make a decision for a small, metastable-prone input signal.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a detection circuit for receiving a pair of unstable input signals along a pair of input leads, such as from a comparator, and providing a stable output signal along an output lead, preferably to downstream circuitry. The detection circuit includes a plurality of transistors including a first transistor and a second transistor, wherein at least one of the first and second transistors is configured to turn on upon the detection circuit receiving input signals along the pair of input leads. At least one of the first and second transistors is configured to provide a signal along a lead to circuitry which is configured to condition the output signal and turn on a third transistor. The third transistor is connected to the first and said second transistors such that when the third transistor turns on, the third transistor prevents the first and second transistors from turning on until a new clock signal is received by the detection circuit. Thus, the third transistor generally prevents any new input signals received along the input leads from propagating substantially through the detection circuit.
Preferably, the first, second and third transistors are n-channel transistors and the feedback circuitry includes a plurality of logic devices such as nor gates, wherein at least one of the logic devices is connected to a pair of output leads. Specifically, preferably an output of a first logic device is connected to an input of a second logic device, and to the third transistor, and an output of the second logic device is connected to an input of the first logic device. Preferably, the anti-propagation circuitry also includes a fourth and fifth transistor which are connected to the first and second transistors. Preferably, the fourth and fifth transistors are p-channel transistors. The first and second transistors are configured to be off while the fourth and fifth transistors are configured to be on if generally equal input signals are received along the input leads. Preferably, the detection circuit is configured to provide that the output leads are low if generally equal input signals are received along the input leads. As such, the detection circuit is configured to hold a previous clock cycle value output at the output lead if generally equal input signals are received along the input leads. Desirably, the detection circuit is configured such that the third transistor turns on upon a differential between the input signals being greater than 2 vts. (approximately 1.3 volts). In addition, the time it takes to attain a decision level is limited to a desired time interval where the differential between the input signals is small.
REFERENCES:
patent: 5306970 (1994-04-01), Phillips
patent: 5872465 (1999-02-01), Saitoh
patent: 5959919 (1999-09-01), Choi
Bitting Rick F.
Savage Scott C.
Lam Tuan T.
LSI Logic Corporation
Trexler, Bushnell Giangiorgi, Blackstone & Marr, Ltd.
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