Comparator input stage for interface with signal current

Details Comparator input stage for interface with signal current Comparator input stage for interface with signal current

1985-10-31

1987-07-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307270, 307491, 307494, 307255, 330257, 330267, H03F 318

Patent

active

046820590

ABSTRACT:
A current interface has an impedance buffering circuit which maintains a very low input impedance at an input node, while producing currents to two current outputs which increase and decrease, respectively, with increases and decreases in the input current flow. In a preferred embodiment, the impedance buffering circuit is an operational amplifier which has been modified to provide access to the collector terminals of a complementary output transistor pair. The collector terminals are connected to current mirrors which are also connected to an output node of the interface circuit. The amplifier and current mirrors effectively buffer the input and reconstruct changes in the input current at the output node, while maintaining a very low input impedance at the input node. Compensation for errors introduced by the changes in base currents of the complementary output pair is provided by a matching pair of complementary transistors.

REFERENCES:
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patent: 3508073 (1970-04-01), Everly et al.
patent: 3509372 (1970-04-01), Bicking
patent: 4152662 (1979-05-01), Sakai et al.
patent: 4251743 (1981-02-01), Hareyama
patent: 4433303 (1984-02-01), Sasaki
patent: 4446443 (1984-05-01), Johnson et al.
patent: 4523105 (1985-06-01), Jose et al.
patent: 4536662 (1985-08-01), Fujii
patent: 4540951 (1985-09-01), Ozawa et al.
patent: 4573019 (1986-02-01), Yamada
patent: 4591739 (1986-05-01), Nagano

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