Comparator for negative and near-ground signals

Details Comparator for negative and near-ground signals Comparator for negative and near-ground signals

2001-09-18

2002-09-10

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C330S261000

Reexamination Certificate

active

06448822

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to comparator circuits, and in particular to high speed comparator circuits having a wide dynamic range.
RELATED ART
A comparator is a circuit that compares two input signals, and generates an output signal that indicates which of the two input signals is larger. Comparator circuits are used, for example, to convert analog input signals into digital values. High speed, accuracy and a wide dynamic range are important characteristics of comparators. However, it is difficult to achieve all three characteristics at the same time.
FIG. 1
is a block diagram showing a prior art comparator circuit
100
that compares two analog input voltages V
IN1
, and V
IN2
, and generates full swing output signals V
OUT1
and V
OUT2
that indicate the larger of input voltages V
IN1
, and V
IN2
. Comparator circuit
100
includes a current source
110
, a differential input circuit
120
, and a CMOS latch
130
. Current source
110
is controlled by a current source bias signal V
CSB
to draw a bias current I
A+B
from differential input circuit
120
. Differential input circuit
120
generates currents I
A
and I
B
that are proportional to input voltages V
IN1
, and V
IN2
, and whose sum is equal to bias current I
A+B
CMOS latch
140
is controlled by clock signals &phgr;
1
and &phgr;
2
to sequentially operate in reset, comparison, and latch operating modes. The reset mode is used to initialize CMOS latch
130
. During the comparison and latch modes, currents I
A
and I
B
are used to set output signals V
OUT1
and V
OUT2
in a first state (V
OUT1
is high and V
OUT2
is low), or a second state V
OUT1
is low and V
OUT2
is high), thereby indicating which of input signals V
IN1
, and V
IN2
is larger. Additional details regarding the operation of comparator circuit
100
are provided below.
FIG. 2
is a simplified schematic diagram showing a CMOS implementation of comparator circuit
100
.
As indicated in
FIG. 2
, current source
110
includes an n-channel transistor M
1
connected between input circuit
120
and ground. A gate terminal of n-channel transistor M
1
is connected to receive an externally generated bias signal VCSB, which is used to set bias current I
A+B
.
Input circuit
120
includes a differential input transistor pair M
2
and M
3
that are connected in parallel between CMOS latch
130
and current source
110
. Current I
A
is generated in a first conductor
122
that is connected between transistor M
2
and a node NA of CMOS latch
130
. Current I
B
is generated on a second conductor
124
that is connected between transistor M
3
and a node NB of CMOS latch
130
. The gate terminals of transistors M
2
and M
3
are respectively connected to input voltages V
IN1
, and V
IN2
.
CMOS latch
130
includes a p-channel flip-flop
132
connected between a system voltage source and nodes NA and NB, an n-channel flip-flop
134
connected between ground and a second pair of nodes NC and ND, a pair of p-channel pass transistors M
6
and M
7
connected between flip-flops
132
and
134
, a p-channel switch M
8
connected between nodes NA and ND, and a pair of n-channel precharge transistors M
11
and M
12
respectively connected to nodes NC and ND. P-channel flip-flop
132
includes p-channel transistors M
4
and M
5
that are respectively connected between the system voltage source and nodes NA and NB, with the gate terminal of transistor M
4
connected to node NB and the gate terminal of transistor M
5
connected to node NA. P-channel pass transistors M
6
and M
7
are controlled by second clock signal &phgr;
2
. P-channel pass transistor M
6
is connected between node NA and node NC (which is connected to output terminal V
OUT1
), and p-channel pass transistor M
7
is connected between node NB and node ND (which is connected to output terminal V
OUT2
). P-channel switch M
8
has a gate terminal connected to receive first clock signal &phgr;
1
. N-channel flip-flop
134
includes n-channel transistors M
9
and M
10
. Transistor M
9
is connected between node NC and ground and has a gate terminal connected to node ND, and transistor M
10
is connected between node ND and ground and has a gate terminal connected to node NC. Precharge transistors M
11
and M
12
have gate terminals connected to receive second clock signal &phgr;
2
, with precharge transistor M
11
connected between node NC and ground, and precharge transistor M
12
connected between node ND and ground.
FIGS.
3
(A) and
3
(B) are timing diagrams showing the voltage levels of clock signals &phgr;
1
and &phgr;
2
during the reset mode (i.e., time interval T
1
-T
2
), comparison mode (i.e., time interval T
2
-T
3
), and latch mode (i.e., time interval T
3
-T
4
) of CMOS latch
130
. During the reset mode (time interval T
1
-T
2
), first clock signal &phgr;
1
is low and second clock signal &phgr;
2
is high. During the comparison mode (time interval T
2
-T
3
), both clock signals &phgr;
1
and &phgr;
2
are high. During the latch mode (time interval T
3
-T
4
), first clock signal &phgr;
1
is high and second clock signal &phgr;
2
is low.
Operation of comparator circuit
100
will now be described with reference to
FIGS. 2
,
3
(A), and
3
(B).
During the reset mode, the low clock signal &phgr;
1
turns on switch M
8
, thereby equalizing nodes NA and NB and resetting p-channel flip-flop
132
. In addition, the high clock signal &phgr;
2
turns off p-channel pass transistors M
6
and M
7
, and turns on n-channel precharge transistors M
11
and M
12
, thereby pulling down nodes NC and ND and resetting n-channel flip-flop
134
to ground (i.e., both output signals V
OUT1
and V
OUT2
are low). Because p-channel pass transistors M
6
and M
7
are turned off, node NA is isolated from node NC, and node NB is isolated from node ND. Under these conditions, the sum of the currents flowing through transistors M
4
and M
5
(i.e., currents I
A
and I
B
) is equal to I
A+B
and is independent of input signals V
IN1
, and V
IN2
(assuming input signals V
IN1
, and/or V
IN2
is/are within the dynamic range). Similarly, during the reset mode, the voltage at nodes NA and NB is equal to a reset voltage that is independent of input signals V
IN1
, and V
IN2
.
At the beginning of the comparison mode (time T
2
in FIGS.
3
(A) and
3
(B)), both clock signals &phgr;
1
and &phgr;
2
are high. Accordingly, first clock signal &phgr;
1
turns off (opens) switch M
8
, thereby disconnecting nodes NA and NB and initiating the operation of p-channel flip-flop
132
. Immediately after time T
2
, if input signal V
IN1
, is less than input signal V
IN2
, then the current through p-channel transistor M
5
is greater than the current through p-channel transistor M
4
, thereby causing the voltage at node NA to increase from the reset voltage and the voltage at node NB to decrease from the reset voltage. Conversely, when input signal V
IN1
is greater than input signal V
IN2
, then the current through p-channel transistor M
5
is less than the current through p-channel transistor M
4
, and the voltage at node NA decreases from the reset voltage while the voltage at node NB increases from the reset voltage.
At the beginning of the latch mode (time T
3
), clock signal &phgr;
2
switches low, thereby turning off precharge transistors M
11
and M
12
, and turning on (closing) pass transistors M
6
and M
7
. The voltage gain between nodes NA and NB, which is caused by the difference between the currents through p-channel transistors M
4
and M
5
of p-channel flip-flop-
132
during the comparison mode, is transferred through pass transistors M
6
and M
7
, respectively, to n-channel flip-flop
134
. If input signal V
IN1
, is less than input signal V
IN2
, then the signal passed through n-channel pass transistor M
6
to node NC is greater than the signal passed through n-channel pass transistor M
7
to node ND, thereby latching flip-flop
134
in a first state (i.e., output signal V
OUT1
is high, and output signal V
OUT2
is low). Conversely, if input signal V
IN1
is greater than i

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