Comparator circuit having a fast recovery time

Details Comparator circuit having a fast recovery time Comparator circuit having a fast recovery time

1988-05-04

1989-11-28

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307491, 307494, 328146, H03K 524

Patent

active

048839876

ABSTRACT:
A multistage comparison circuit (10) having a cascaded chain of capacitively coupled comparators (34) is disclosed. A reset mode of operation (54) imposes a common mode voltage on the input of the comparators (34). Consequently, capacitors (22, 24) which couple the comparators (34) together are charged to compensate for errors so that a high precision comparison may result. A shorting switch (40) couples across differential outputs (36, 38) of the comparators (34) and is momentarily activated prior to each bit comparison (71) in a word comparison mode (70) of operation. This shorting takes the comparators (34) out of saturation and places the comparison circuit (10) in a state which approximates the reset state. Specific comparator architectures are disclosed which force approximately equal currents to be fed into the output nodes (36, 38) and which dynamically adjust output offset voltage and feedthrough errors so that the shorted condition accurately approximates the reset condition.

REFERENCES:
patent: 4511810 (1985-04-01), Yukawa
Allstot, "A Precision Variable-Supply CMOS Comparator", IEEE Journal of Solid-State Circuits, vol. SC-17, No. 6, Dec. 1982, pp. 1080-1087.

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