Comparator circuit for a C-2C A/D and D/A converter

Details Comparator circuit for a C-2C A/D and D/A converter Comparator circuit for a C-2C A/D and D/A converter

1976-04-02

1978-06-27

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307DIG3, 328162, 340347AD, 340347CC, 365 45, 365210, 365228, H03K 520

Patent

active

040977536

ABSTRACT:
A comparator circuit for comparing two voltage levels in a C-2C A/D and D/A converter, comprising four cross-coupled active devices (FETs) in a latch arrangement whereby an offset voltage is used to compensate for imbalances in the comparator. The comparator includes a first FET having its gate electrode connected to the output of the D/A converter, and a second FET having its gate electrode connected to an analog input voltage. The first and second FETs each have one of their electrodes connected to a common voltage source. A third and a fourth FET have one of their electrodes connected respectively to the other electrode of the first and second FETs at first and second common nodes, respectively. The output of the comparator is provided at one of such first and second common nodes. The first and second nodes are also respectively connected to the gate electrodes of the fourth and third FETs in a cross-coupled arrangement. The other electrode of both the third and fourth FETs are connected to a common phase voltage source. An offset voltage is generated at the input to either of the gate electrodes of the first and second FETs to set the comparator at a balance point and thereby compensate for the differences in the threshold voltages and current carrying capabilities of the four FETs. Also, the comparator has relatively high input impedance, gain and bandwidth.

REFERENCES:
patent: 3573794 (1971-04-01), Widenor
patent: 3811125 (1974-05-01), Schumann
patent: 3908181 (1975-09-01), Shigaki et al.
patent: 3916314 (1975-10-01), Franaszek et al.

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