Comparator circuit and method thereof

Details Comparator circuit and method thereof Comparator circuit and method thereof

1995-05-01

1996-06-11

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 63, 327 71, H03K 522

Patent

active

055259200

ABSTRACT:
Comparator circuit (72) samples a differential input signal at switched capacitor circuit (100). The input signal is stored across capacitors (128, 130, 132, 134). Reference voltages are subtracted from the input signal to produce a difference signal. The difference is compared to a mid-supply reference VMID, and an amplified representation of the signal is produced at the output of differential gain stage (136). Latching output stage (138) uses feedback circuits (204, 211 and 202, 208) to process the amplified signal and to produce a rail to rail representation of the amplified signal at the inputs (146, 148) of SR latch (140). The feedback circuit also powers-down the output stage after processing the amplified signal. Buffer circuits (205, 213 and 214, 212) allow a new signal to be processed by capacitor circuit (100) while the previous signal is being stored in the SR latch.

REFERENCES:
patent: 4523107 (1985-06-01), Peterson
patent: 4539551 (1985-09-01), Fujita et al.
patent: 4546324 (1985-10-01), Bingham et al.
patent: 4710724 (1987-12-01), Connell et al.
patent: 4803462 (1989-02-01), Hester et al.
patent: 5302869 (1994-04-01), Hosotani et al.
patent: 5362996 (1994-11-01), Lin
"A 10-bit, 20-MS/s, 35-mW Pipeline A/D Converter," by Cho et al., IEEE 1994 Custom Integrated Circuits Conference, pp. 499-502.

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