Comparator circuit and method of operating a comparator circuit

Details Comparator circuit and method of operating a comparator circuit Comparator circuit and method of operating a comparator circuit

2003-10-10

2004-12-14

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S169000, C341S170000, C341S155000

Reexamination Certificate

active

06831586

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to field of analog-to-digital conversion, and more specifically, to a comparator for an analog-to-digital converter, and to a method of operating a comparator circuit.
High speed or low latency analog-to-digital converters (ADC's) need a fast comparator design. In many cases this means that a comparator using a bipolar latch would be advantageous. However, the circuits receiving the comparator output are often implemented in CMOS and hence CMOS output levels of the comparator are desired. Using circuit techniques known today for implementing a level shift from the bipolar latch signal swing of about 0.7 volt to the full power supply signal swing of CMOS with only an insignificant additional delay will require a large power consumption. Such large power consumption can usually not be tolerated or is not desired.
Feeding the 0.7 voltage swing directly to a CMOS buffer will cause two problems to arise. Firstly, the matching of the common mode voltage of the bipolar output to the threshold of the CMOS inverter will depend on absolute values of the different components and will not give a reliable matching. Secondly, the input drive of the CMOS inverter will only be in the order of 0.7/2 volts, which due to the poor MOS transistor transconductance will cause the inverter to only deliver a smaller output current and hence the delay will be undesirably large.
To overcome such problems various comparator circuits have been proposed. In
FIG. 1
is shown an example of such a comparator circuit. The
FIG. 1
circuit provides CMOS output levels and has the potential of operating at high speed due to the short time constant of the regenerative bipolar latch formed by transistors Q
1
and Q
2
. The nMOS transistors M
1
and M
2
form an input suitable for switched capacitor circuits. Resistors R
1
and R
2
comprise a load for the input stage in the preamplification phase when clock &PHgr; is low, and for the bipolar latch during comparison phase starting when &PHgr; goes high. The bipolar latch is buffered by emitter followers Q
3
and Q
4
to not degrade the regeneration time constant by the load of the differential stage Q
5
and Q
6
, which would slow down the response. The differential stage steers the current 2×I
3
to either the current mirror M
5
, M
6
or to the current mirror M
7
, M
8
depending on the latch decision. Consequently, the node voltages a
+
and a
−
will go in opposite direction to high and low levels depending on the current steering. The desired drive capability is then supplied by buffers B
1
and B
2
.
The comparator in
FIG. 1
represents a frequently used technique, wherein the common mode voltage of the bipolar latch output will be of less concern since it is interfaced by the differential stage Q
5
and Q
6
. Also, due to the use of bipolar transistors, even the low ±0.7 volt differential swing will be adequate to fully direct the 2×I
3
current. The delay to nodes at is then dependent on the ratio between the parasitic capacitors C
±
and the bias current I
3
, which can be chosen arbitrarily within certain ranges. Thus, an increased speed is obtained at the cost of increased power consumption. The slew rate also improves with low load capacitance, which means that the buffers should have a small input capacitance. Consequently, an increased number of buffer stages may be necessary to provide sufficient drive, but which indeed add further delay to the comparator.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a comparator circuit for an analog-to-digital converter, which uses a bipolar latch to obtain an adequate speed, and which provides an output suitable to be used in CMOS circuitry.
In this respect there is a particular object of the invention to provide such a comparator circuit, which provides for a fast level shift at an insignificant increase in power consumption.
A further object of the present invention is to provide such a comparator circuit with high drive capability, which reduces the amount of output buffering needed.
Still a further object of the present invention is to provide such a comparator circuit, which is accurate, precise, efficient, simple, and of low cost.
These objects among others are attained by a comparator circuit comprising an input stage, preferably a differential stage, for receiving an input signal; a bipolar latch stage, preferably consisting of a pair of bipolar transistors, coupled to the input stage for performing a latch decision based on the input signal; means for amplifying the latch output to a level suitable for CMOS circuitry; and an output, possibly a differential output. According to the invention the means for amplifying includes at least one and preferably two tapping transistors, preferably bipolar transistors, coupled to the latch stage for, depending on the latch decision, tapping a collector current from the latch stage, while leaving the latch decision thereof unaffected, such that a current gain of the latch stage can be used to amplify a latch bias current of the latch stage to thereby provide for the amplification.
By amplifying the latch bias current to a considerably larger current, which current is used to toggle the state of the output, a higher voltage swing than the swing of the latch stage itself, is provided.
An inventive analog-to-digital converter comprises a plurality of the above described comparator circuit.
Still a further object of the present invention is to provide a method of operating a comparator for an analog-to-digital converter, which provides an output suitable to be used in CMOS circuitry, and which provides for a fast comparison at low power consumption.
These objects among others are attained by a method wherein:
(i) an input signal, preferably a differential signal, is fed to a differential input stage;
(ii) a latch decision is performed based on the input signal in a bipolar latch stage coupled to the input stage, and an output signal, preferably a differential output signal, depending on the decision is output therefrom;
(iii) the output signal is amplified to a level suitable to be input to CMOS circuitry; and
(iv) the amplified output signal is output through an output.
The method comprises the inventive features that depending on the latch decision a collector current is tapped from the latch stage, while the latch decision thereof is left unaffected, by means of a tapping or level shift transistor coupled to the bipolar latch stage; and a current gain of said bipolar latch stage is used to amplify a latch bias current of the bipolar latch stage to thereby provide for the amplification of the output signal.
The present invention uses the excessive drive capability of the bipolar latch stage to discharge level shifting nodes located at the output side of the tapping or level shift transistor and thus a large output swing is achieved with low delays and low power consumption. The output swing is readily matched to the full power supply signal swing of CMOS circuitry.
Further characteristics of the invention and advantages thereof will be evident from the detailed description of preferred embodiments of the present invention given hereinafter and the accompanying
FIGS. 1-8
, which are given by way of illustration only, and thus are not limitative of the present invention.


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