Comparator circuit and method

Details Comparator circuit and method Comparator circuit and method

2006-09-05

2006-09-05

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C340S146200

Reexamination Certificate

active

07103624

ABSTRACT:
A binary comparator circuit and a binary data comparison method for reducing a layout area and power consumption and/or increasing comparison speed. The binary data comparison circuit and method receive all N bits of each of a first binary data An−1An−2. . . A1A0and a second binary data Bn−1Bn−2. . . B1B0, and compare the first binary data and the second binary data to determine which of the first binary data and the second binary data is larger according to the following equation:in-line-formulae description="In-line Formulae" end="lead"?F(A≦B)=A(n−1)′·B(n−1)+(A(n−1)′+B(n−1))·{A(n−2)′·B(n−2)+(A(n−2)′+B(n−2)) . . . {A1′·B1+(A1′+B1)·(A0′+B0)}}in-line-formulae description="In-line Formulae" end="tail"?where subscripts denote a position of a bit of the N-bit binary data and a prime (′) indicates that a bit is inverted, and outputting a signal corresponding to the comparison result.

REFERENCES:
patent: 4728927 (1988-03-01), Aman
patent: 4933662 (1990-06-01), Szczepanek
patent: 5281946 (1994-01-01), Van Le
patent: 6014074 (2000-01-01), Park
patent: 6177862 (2001-01-01), Sakata

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