Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Patent
1988-10-18
1991-04-23
Pellinen, A. D.
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
307355, 307362, H03K 524, H03M 136
Patent
active
050103385
ABSTRACT:
A comparator circuit capable of high-speed and accurate operation is disclosed. The comparator circuit includes an amplifier section 4, an inverter 5 connected to the output of the amplifier section 4, and a switching circuit 11 connected across the inverter 5. The amplifier section 4 contains a capacitor 1, an inverter 2 and a switching circuit 3 connected across the inverter 2. Coupled to the input of the amplifier section 4 are switching circuits 8 and 9 for supplying voltages V.sub.1 and V.sub.2 to be compared under timing control. During the first half cycle of comparing operation, the switching circuits 8, 3 and 11 are turned on while the switch circuit 9 is turned off. During the second half cycle of comparing operation, the switching circuit 9 is turned on while the switching circuits 8, 3 and 11 are turned off. The inverter 5, being short circuited by the switching circuit 11, produces a predetermined intermediate voltage during the first half of operating cycle, which is effective to generate voltage outputs accurately and exactly representing the compared results during the second half of the operating cycle.
REFERENCES:
patent: 4507649 (1985-03-01), Dingwall et al.
patent: 4532438 (1985-07-01), Reiner
patent: 4539551 (1985-09-01), Fujita et al.
patent: 4612531 (1986-09-01), Dingwall et al.
patent: 4691189 (1987-09-01), Dingwall et al.
patent: 4695748 (1987-09-01), Kumamoto
IEEE Journal of Solid State Circuits, vol. SC-21, No. 6, Dec. 1986: "An 8-Bit High-Speed CMOS A/D Converter".
"CMOS 8b 25MHz Flash ADC", Digest of Technical Papers, IEEE International Solid-State Circuits Conf., 1985.
Hosotani Shiro
Miki Takahiro
Logan Sharon D.
Mitsubishi Denki & Kabushiki Kaisha
Pellinen A. D.
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