Oscillators – Relaxation oscillators
Reexamination Certificate
2000-03-30
2002-09-24
Kinkead, Arnold (Department: 2817)
Oscillators
Relaxation oscillators
C331S111000, C327S050000, C327S054000, C327S056000, C327S057000
Reexamination Certificate
active
06456170
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a comparator, and in particular to a comparator adapted to control the threshold voltage of an inverter. Furthermore, this invention relates to a voltage controlled oscillator circuit, and in particular to a voltage controlled oscillator circuit which oscillates at a high frequency.
BACKGROUND OF THE INVENTION
Comparators are used in analog circuits such as VCO (voltage controlled oscillator circuits) forming PLL (phase-locked loops) which are used in portable radio devices and for clock frequency conversion. Recently, speed of analog circuits is increasing more and more. As a result, a short delay time and a high speed characteristic are required of comparators.
Voltage controlled oscillator circuits are used as components of PLL (phase-locked loops) used in portable radio devices and for clock frequency conversion. Sometimes the voltage controlled oscillator circuit incorporates two comparators. The oscillation frequency of the voltage controlled oscillator circuit is influenced by the delay time of the incorporated comparator. Accordingly, for obtaining a voltage controlled oscillator circuit having a high oscillation frequency, it is necessary to use a comparator which operates at high speed.
FIGS. 1
,
2
and
3
shows circuit symbol, circuit, and output characteristic of a conventional comparator of inverter type, respectively. The conventional comparator
11
is formed of a CMOS inverter including a PMOS transistor Q
1
and an NMOS transistor Q
2
. Input voltage Vin is input into gates of these transistors Q
1
and Q
2
. Output voltage Vout is output from the drains of the transistors Q
1
and Q
2
connected in common.
This comparator
11
formed of the CMOS inverter has an operation delay time of a few nanoseconds, which is quite short, and therefore it operates at a high speed. Reference voltage of the comparator
11
, i.e., a voltage serving as a reference voltage for comparing the magnitude of the input voltage is the threshold voltage of the transistors Q
1
and Q
2
. When the input voltage Vin is lower than the threshold voltage Vth as shown in
FIG. 3
, the PMOS transistor Q
1
turns on and consequently the output voltage Vout becomes “H” level which is relatively high in potential. On the other hand, when the input voltage Vin is higher than the threshold voltage Vth, NMOS transistor Q
2
turns on and consequently the output voltage Vout becomes “L” level which is relatively low in potential.
FIGS. 4
,
5
and
6
shows a circuit symbol, circuit, and output characteristic of a conventional differential comparator, respectively. This comparator
12
has a configuration obtained by combining a differential amplifier circuit with a single-ended amplifier circuit. The differential amplifier circuit includes PMOS transistors Q
3
and Q
4
, NMOS transistors Q
5
and Q
6
, and a current source
13
. The single-ended amplifier circuit includes a PMOS transistor Q
7
and an NMOS transistor Q
8
.
Gates of the NMOS transistors Q
5
and Q
6
are supplied with a reference voltage VR and an input voltage Vin, respectively. A drain output of the transistor Q
6
is input into gates of the PMOS transistor Q
7
and the NMOS transistor Q
8
. Output voltage Vout is output from the drains of the transistors Q
7
and Q
8
connected in common.
Since the differential amplifier circuit is used in this differential comparator
12
, the input voltage Vin can be compared with the reference voltage VR accurately. In other words, when the input voltage Vin is lower than the reference voltage VR, then the drain output of the transistor Q
6
is “H” level, the NMOS transistor Q
8
turns on, and therefore the output voltage Vout becomes “L” level as shown in FIG.
6
. On the other hand, when the input voltage Vin is higher than the reference voltage VR, then the drain output of the transistor Q
6
is “L”level, the PMOS transistor Q
7
turns on, and therefore the output voltage Vout becomes “H” level.
FIG. 7
is a circuit diagram of a conventional comparator of chopper type (hereinafter, comparator). This comparator includes inverter
14
, capacitor
15
, latch circuit
16
, and first through third switches
17
,
18
and
19
. The first and second switches
17
and
18
are controlled by a clock signal &PHgr; so as to turn on/off. The third switch
19
is controlled by an inverted signal /&PHgr; of the clock signal &PHgr; (where “/” represents a bar indicating inversion) so as to turn on/off.
FIG. 8
is an operation timing diagram of the chopper comparator shown in FIG.
7
. When the clock signal &PHgr; is “H” level (in other words, when /&PHgr; is “L” level), the first and second switches
17
and
18
turn on, resulting in auto zero operation. During the period when this auto zero operation is being carried out, voltages V
1
and V
2
respectively at nodes located on input and output sides of the inverter
14
become a threshold voltage Vth of the inverter, and a potential difference between this threshold voltage Vth and the reference voltage VR is stored in the capacitor
15
.
When the clock signal &PHgr; is “H” level (in other words, when /&PHgr; is “H” level), the third switch
19
turns on and a comparison operation is performed. During the period when this comparison operation is being carried out, if the input voltage Vin is higher than the reference voltage VR then the output voltage V
2
of the inverter
14
becomes “L” level. In synchronism with the next rising edge of the clock signal, this is output from the latch circuit
16
as an output voltage Vout of “L” level. On the other hand, during the period the comparison operation is being carried out, if the input voltage Vin is lower than the reference voltage VR then the output voltage V
2
of the inverter
14
becomes “H” level. In synchronism with the next rising edge of the clock signal, this is output from the latch circuit
16
as an output voltage Vout of “H” level.
FIG. 9
is a circuit diagram of an oscillator circuit comprising two comparators. This oscillator circuit
2
includes first and second comparators
21
a
and
21
b
, capacitor
22
charged or discharged to supply a comparison voltage Vc to the first and second comparators
21
a
and
21
b
, first and second current sources
23
a
and
23
b
for charging or discharging the capacitor
22
, first and second switches
24
a
and
24
b
and inverter
25
for respectively controlling on/off of the first and second current sources
23
a
and
23
b
, and latch circuit composed of two NAND gates
27
a
and
27
b
for latching a signal obtained by inverting an output signal of the first comparator
21
a
by means of inverter
26
and an output signal of the second comparator
21
b
and outputting an oscillation signal as an output voltage Vout.
The first comparator
21
a
is supplied with a voltage signal which is relatively high in potential (hereafter referred to as high reference voltage VRH) as a reference voltage. The second comparator
21
b
is supplied with a voltage signal which is relatively low in potential (hereafter referred to as low reference voltage VRL) as a reference voltage. The first switch
24
a
is controlled by the output signal of the latch circuit, i.e., the oscillation signal. The second switch
24
b
is controlled by a signal obtained by inverting the oscillation signal using the inverter
25
.
FIG. 10
is an operation timing diagram of the oscillator circuit
2
shown in FIG.
9
. When a terminal voltage VC, the voltage that increases due to charging, of the capacitor
22
exceeds the high reference voltage VRH, the first comparator
21
a
performs comparison operation after a delay time td. As a result, an output voltage of the inverter
26
(a voltage at a node A located on an output side of the inverter
26
) supplied with an output signal of the comparator
21
a
is switched from “H” level to “L” level. Accordingly, the latch circuit is reset, and the output voltage Vout of the latch circuit is switched from “H” level to “L” level.
Furthermore, when the terminal voltage of the capacitor
Haga Akira
Kikuchi Osamu
Otsuka Masaru
Segawa Yuji
Yoshikawa Yoshinori
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
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