Comparator and analog-to-digital converter

Details Comparator and analog-to-digital converter Comparator and analog-to-digital converter

2002-05-20

2003-09-23

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S063000, C327S065000

Reexamination Certificate

active

06624667

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a comparator for comparing a signal voltage with a reference voltage. More particularly, it relates to a comparator with a reduced number of circuit components and an analog-to-digital converter having the comparator.
2. Description of the Related Art
As for a flash-type analog-to-digital converter for fast coding input analog signals to convert them into the digital form, the configuration shown in
FIG. 1
is known as a conventional example. As shown in
FIG. 1
, a conventional analog-to-digital converter is configured: to compare input voltages from an analog signal input terminal
41
with the n levels of reference voltages, which is produced in a resistor ladder
42
by dividing a potential difference between the upper-potential reference voltage VRH and lower-potential reference voltage VRL, using comparators
61
-
6
n
; to store the results of the comparisons in data holding circuits
71
-
7
n
; and to convert the stored results into coded digital signals using an encoder
43
to output the signals from a digital signal output terminal
44
.
In general, the comparators
61
-
6
n
are chopper type comparators, and the data holding circuits
71
-
7
n
are each arranged as shown in FIG.
2
. An input data from a data input terminal
81
passes through a switch
82
, which is closed when data is stored, and enters a master flip-flop composed of inverters
83
,
84
connected so as to perform a positive feedback. An output of the master flip-flop passes through a switch
85
, which is opened and closed in opposite phase to the switch
82
, and enters a slave flip-flop composed of inverters
86
,
87
connected so as to perform a positive feedback. Then, an output data from the slave flip-flop is output from a data output terminal
88
.
In recent years, as a circuit scale has been enlarged for a multi-bit-capable analog-to-digital converter with high-accuracy, the reduction of the number of circuit components has been required to downsize the layout-scale thereof. Trying to constitute an 8-bit flash-type analog-to-digital converter, for example, in the case of
FIG. 1
requires 255 comparators and the same number of, i.e. 255, data holding circuits because n=255. Therefore, the problem of the use of vast numbers of components as a whole arises when constituting an analog-to-digital converter by combining comparators and data holding circuits simply.
SUMMARY OF THE INVENTION
The invention was made in consideration of the foregoing problems, and intended to provide a comparator with a reduced number of circuit components and thereby to provide an analog-to-digital converter with a reduced number of circuit components.
A comparator in a basic configuration according to the invention includes: a selecting unit for selectively outputting a signal voltage and a reference voltage; a first capacitor having one end for receiving an output from the selecting unit; a first inverter having an input connected to the other end of the first capacitor; a first switch provided between the input and output of the first inverter; a tri-state inverter having an input connected to the output of the first inverter; a first latch unit having an input connected to the output of the tri-state inverter; and a second switch having one end provided between the output of the first latch unit and an input of a second latch unit.
Use of a comparator in the basic configuration according to the invention eliminates the need for a switch which is provided between the output of the comparator and a first latch unit traditionally in the related art, whereby the number of components in a data holding section (holding portion for storing an output voltage from a comparator) can be reduced.
In a comparator in the basic configuration according to the first embodiment of the invention, the first and second switches are closed and the output of the first tri-state inverter becomes a high impedance state when the selecting unit selects the signal voltage; and the first and second switches are opened and the first tri-state inverter operates as an inverter when the selecting unit selects the reference voltage.
In a comparator in the basic configuration according to the second embodiment of the invention, the first and second switches are closed and the output of the tri-state inverter becomes a high impedance state when the selecting unit selects the signal voltage; the first switch is opened when the selecting unit selects the reference voltage; and after the first switch becomes an opened state, the tri-state inverter is changed from the state where the output thereof has a high impedance to a state operable as an inverter and the second switch changes from the closed state to the opened state.
Use of a comparator according to the second embodiment of the invention, besides the advantage of a comparator in the basic configuration, allows reduction in flow-through current of the tri-state inverter in comparison to the first embodiment.
A comparator according to the third embodiment of the invention includes: a third switch provided between an output for a signal voltage and one end of a first capacitor; a first inverter having an input connected to the other end of the first capacitor; a first switch provided between the input and an output of the first inverter; a tri-state inverter having an input connected to the output of the first inverter; a first latch unit having an input connected to an output of the tri-state inverter; a second switch provided between an output of the first latch unit and an input of a second latch unit; a fourth switch provided between an output for a reference voltage and one end of a second capacitor; a fourth inverter having an input connected to the other end of the second capacitor; a fifth switch provided between the input and an output of the fourth inverter; a sixth switch provided between the one end of the first capacitor and the one end of the second capacitor; a seventh switch and a third capacitor connected in series between the input of the first inverter and the output of the fourth inverter; and an eighth switch and a fourth capacitor connected in series between the input of the fourth inverter and the output of the first inverter, wherein the signal voltage and reference voltage are simultaneously output to the one end of the first capacitor and to the one end of the second capacitor respectively while the seventh and eighth switches are turned on, and further the first switch is turned on to hold a difference voltage between the signal voltage and an offset voltage of the first inverter on both ends of the first capacitor, and the fifth switch is turned on to hold a difference voltage between the reference voltage and an offset voltage of the fourth inverter on both ends of the second capacitor, after the signal voltage and reference voltage are simultaneously output to the one end of the first capacitor and to the one end of the second capacitor respectively, the third, fourth, seventh, eighth switches are turned off while the sixth switch is turned on and the first and fifth switches are turned off to amplify approximately one half voltage of a difference voltage between the signal voltage and reference voltage using the first inverter, and after the first and fifth switches are turned off, the seventh and eighth switches are turned on while the tri-state inverter operates as an inverter to output an output voltage of the first inverter on the output of the tri-state inverter.
Use of a comparator according to the third embodiment of the invention, besides the advantage of a comparator in the basic configuration, makes it possible to provide a comparator with less current consumption in comparison to the first embodiment, lower noise in comparison to the second embodiment, and poor sensitivity to the in-phase noise.
According to the fourth embodiment of the invention, an analog-to-digital converter includes: a plurality of comparators in the basic configuration for receiving an

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