Comparator

Details Comparator Comparator

1999-10-14

2001-05-15

Tokar, Michael (Department: 2819)

Communications: electrical

Digital comparator systems

Reexamination Certificate

active

06232872

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to logic circuitry, and in particular, to a comparator.
BACKGROUND INFORMATION
A 64-bit comparator is built in a 4-way merge architecture to reduce the number of logic stages. Conventional ways of 4-way merge for a comparator are based on equations:
EQ
(
i
)=
A
(
i
)
B
(
i
)+
A
—
B
(
i
)
B
—
B
(
i
)
GT
(
i
)=
A
(
i
)
B
—
B
(
i
)
LT(i)=A_B(i)B(i)
EQ
4(
i
)=
EQ
(
i
)
EQ
(
i+
1)
EQ
(
i+
2)
EQ
(
i+
3)
GT
4(
i
)=
GT
(
i
)+
EQ
(
i
)
GT
(
i+
1)+
EQ
(
i
)
EQ
(
i+
1)
GT
(
i+
2)+
EQ
(
i
)
EQ
(
i+
1)
EQ
(
i+
2)
GT
(
i+
3)
LT
4(
i
)=
LT
(
i
)+
EQ
(
i
)
LT
(
i+
1)+
EQ
(
i
)
EQ
(
i+
1)
LT
(
i+
2)+
EQ
(
i
)
EQ
(
i+
1)
EQ
(
i+
2)
LT
(
i+
3)
where A, B, A_B, and B_B are true and complemented inputs, EQ stands for EQuivalent, LT stands for Less Than, and GT stands for Greater Than. The above equations involve a 4-way AND, and the total number of logic stages is 4 assuming that the maximum number of transistors allowed on an N stack is 4, which is usually the case.
Such a comparator is often utilized in execution units in a microprocessor or a microcontroller. Chip designers are always searching for new designs that offer faster computation times to thereby increase the throughput of the processor. If a particular circuit or macro can be made faster, then it is often possible to increase the throughput in other circuits or macros. Therefore, what is desired is a faster 64-bit comparator.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing need by providing a faster comparator that is implemented in three logic stages by making efficient use of compound dynamic gates.
A 64-bit comparator includes a first stage for receiving a 64-bit number A and a 64-bit number B, and generating first output values. A second stage then receives the first output values from the first stage and outputs second output values, and a third stage receives the second output values from the second stage and outputs greater than, less than, and equivalent values.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


REFERENCES:
patent: 4225849 (1980-09-01), Lai
patent: 5630160 (1997-05-01), Simpson et al.
patent: 5978305 (1999-11-01), Sasaki et al.
patent: 6046669 (2000-04-01), Giamei et al.
patent: 6054918 (2000-04-01), Holst

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