Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-13
2004-12-28
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185220
Reexamination Certificate
active
06836435
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The subject invention relates generally to the operation of a semiconductor nonvolatile memory (NVM) and, in particular, to a method of erasing an NVM so as to more tightly control the value of the threshold voltage imparted to the NVM cell as a result of an erase operation.
2. Related Art
Semiconductor NVMs, and particularly electrically erasable, programmable read-only memories (EEPROMs), exhibit widespread applicability in a range of electronic equipments from computers, to telecommunications hardware, to consumer appliances. In general, EEPROMs serve a niche in the NVM space as a mechanism for storing firmware and data that must be refreshed periodically in situ. The EEPROM's precursor, the EPROM, can be erased only through UV irradiation and therefore requires removal from its target system prior to erasure. The flash EEPROM may be regarded as a specifically configured EEPROM that may be erased only on a global or sector-by-sector basis. The typical flash EEPROM may be divided into sectors of 64K (65, 536) words. The sacrifice in flash EEPROM erase selectivity is exchanged for a simplified memory cell design, which, in the limit, may require only a single MOS transistor.
As is well known to those skilled in the art, NVM cells are typically constructed by forming a field effect transistor (FET) in a body of semiconductor material, usually silicon. In one configuration, the FET can be made to store electrical charge (holes or electrons) in a separate gate electrode, referred to as a floating gate. Alternatively, in the SONOS NVM cell architecture, the gate structure includes an oxide-nitride-oxide (ONO) dielectric stack. Charge is stored in the nitride layer that is separated from the silicon substrate by a bottom oxide layer and from a polysilicon gate conductor by a top oxide layer. In addition, the Q-flash NVM cell is predicated on a layer of isolated polycrystalline storage islands that are formed underneath a control gate electrode.
Data is stored in an NVM cell by modulating the threshold voltage, V
T
, of the FET through the injection of charge carriers into the charge-storage layer from the channel of the FET. For example, with respect to an N-channel, enhancement-mode FET, an accumulation of electrons in the floating gate, or in a dielectric layer above the FET channel region, causes the FET to exhibit a relatively high V
T
. When the FET control gate is biased to the voltage required to read stored data, i.e., to a “READ” voltage, the FET will fail to conduct current because its then-existing threshold voltage is greater than the voltage applied to the gate. The nonconductive state of the FET may, by convention, be defined and detected as a logic level ONE. Conversely, a reduction in the concentration of electrons in the floating gate or in the nitride layer of a SONOS cell, or in the isolated island storage layer of a Q-flash cell, will cause the FET threshold voltage to diminish, and, in some designs, become negative with respect to ground. In this case, applying the READ voltage to the FET control gate will cause the FET to conduct current from drain to source. In some designs, the FET V
T
may be made negative so that an applied READ voltage of 0V will nonetheless be sufficient to cause current conduction by the FET. Current conduction by the FET may be defined and detected as a logic level ZERO. (It should be noted that NVM systems are also designed to adopt an opposite logic convention in which enduction corresponds to a logic ONE and nonconduction corresponds to a logic ZERO.)
The EEPROM is encountered in numerous configurations. In general, those configurations may be classified according to (i) the nature (i.e., thickness and composition) of the layer used to store charge for V
T
modulation and (ii) the number of operative gate electrodes available to control the operation of the NVM cell. In particular, a floating-gate NVM cell is characterized by a stacked gate construction in which a floating gate, typically formed from polysilicon, is separated from the substrate by a first (lower) oxide layer and is separated from a polysilicon control gate by a second (upper) oxide layer. No direct electrical connection is made to the floating gate (hence, “floating”).
In the operation of an EEPROM, it is regularly required that all or portion of the NVM be programmed (or re-programmed). Typically, a programming operation is anticipated by global erasure of all NVM cells in an array or in a sector. Physically, erasure of an NVM cell constitutes the neutralization of charge stored in the floating gate. In the case where an N-channel, enhancement-mode FET is assumed as the operative NVM cell technology, then erasure is effected by the injection of holes into the floating gate, or by the tunneling of electrons out of the floating gate, so as to neutralize electrons that had previously accumulated in charge-storage sites as a result of a programming operation.
Electrically, an erase operation is intended to impart to the NVM cell a reduced V
T
. An ideal global erase procedure would leave all erased NVM cells in a block with an identically low V
T
. However, in practice it is found that a global erase operation results in an approximately binomial distribution of cell erased threshold voltages, with cells having respective erased threshold voltages that are either higher or lower than the target erased V
T
. As might be expected, the variance in erased threshold voltages is most troublesome at the extremities of the distribution. Because it will persist as nonconductive when the specified READ voltage is applied, an NVM cell with a high erased V
T
may be read speciously as a logic ONE. Conversely, an NVM cell with a low erased V
T
may remain somewhat conductive, even though unselected, thereby contributing to undesirable column leakage current. Furthermore, an over-erased NVM will present an excessive current load during programming, which may in fact lead to programming failures. Accordingly, numerous attempts have been made to circumvent deleterious operational effects that attend the often broad distribution of erased V
T
values of the cells in an NVM array.
In one approach, a “soft” programming step is performed subsequent to erasure of an NVM cell. That is, a positive bias voltage is briefly applied to the gates of cells in a manner that mildly stimulates hot-electron injection into the charge-storage layer of the NVM cell. Current limiting may be a component of a soft programming step. The essence of soft programming is to effect a limited increase in the threshold voltages of erased NVM cells so as to mitigate column leakage current of programmed cells and to preclude the leakage current contributed by unselected cells during a read operation. However, soft programming is deemed a less than optimal response to erasure anomalies in that it broadens the distribution in erased V
T
. That is, no convergence of cell erased V
T
threshold voltage is achieved because soft programming merely shifts the threshold voltages of all cells toward the high-threshold direction. In addition, this approach requires bit-by-bit selection, which significantly slows the erase time.
Another attempt to remediate the distribution in erased V
T
requires the generation of two disparate, and selectable, erase threshold values, EVT
1
and EVT
2
, respectively. When the erased threshold value is set at EVT
2
, the lower limit of the distribution in V
T
after an erase operation is higher than an over-erase threshold value, OEVT. When the erase threshold value is set at EVT
1
, the lower limit of the V
T
distribution after erase is EVTL, a value greater than OEVT. The applicable erase verify threshold values, EVT
1
and EVT
2
, are switched depending on the operating mode of the memory array. During a program/erase test sequence, the applicable erase verify threshold value is EVT
2
. During normal operation, the applicable erase verify threshold value is EVT
1
. See U.S. Pat. No. 6,236,609, Nonvolatile Semiconductor Memory.
Anot
Freescale Semiconductor Inc.
Nguyen Tan T.
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