Compact virtual ground diffusion programmable ROM array...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185050, C365S063000

Reexamination Certificate

active

07929347

ABSTRACT:
A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.

REFERENCES:
patent: 5789776 (1998-08-01), Lancaster et al.
patent: 6195287 (2001-02-01), Hirano
patent: 6920058 (2005-07-01), Morikawa

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